The Xputer is a design for a reconfigurable computer , proposed by scientist Reiner Hartenstein. Hartenstein uses various terms to describe the various innovations in the design, including config-ware, flow-ware, morph-ware, and “anti-machine”.
The Xputer represents a move away from the traditional Von Neumann computer architecture, to a coarse-grained “soft Arithmetic logic unit (ALU)” architecture.  Parallelism is achieved by configurable elements known as reconfigurable datapath arrays (rDPA), organized in a two-dimensional array of ALUs similar to the KressArray .   
The Xputer architecture is data-stream-based, and is the counterpart of the Neumann computer architecture -based instruction .
The Xputer architecture is one of the first coarse-grained reconfigurable architectures,  and consists of a reconfigurable datapath array (rDPA) organized as a two-dimensional array of ALUs (rDPU).  The bus-width between ALUs was 32-bit in the first version of the Xputer. 
The ALUs (also known as rDPUs) are used for computing a single mathematical operation, such as addition, subtraction or multiplication, and can also be used purely for routing. 
ALUs are mesh-connected via three types of connections, and data-flow along these links are managed by an address generation unit. 
- Nearest neighbor (connections between neighboring ALUs)
- Row / column back-nozzles
- Global bus (a single global bus for interconnection between further ALUs)
Programs for the Xputer are written in the C language, and compiled for use on the Xputer using the CoDeX compile written by the author.  The CoDeX compiles maps suitable portions of the C program onto the Xputer’s rDPA fabric.  The remainder of the program is executed on the host system, such as a personal computer .
A reconfigurable datapath array (rDPA) is a semiconductor device containing reconfigurable data and programmable interconnects, first proposed by Rainer Kress in 1993, at the University of Kaiserslautern .
Instead of FPGAs ( field-programmable gate arrays ) having configurable single bit logic blocks (CLBs), rDPAs have multiple bits wide (for instance, 32 bit path width) reconfigurable datapath units (rDPUs).
Each rDPU can be configured to perform an individual function. These rDPUs and interconnects can be engineered by the customer / designer (hence the term “reconfigurable”) so that the rDPA can perform whatever complex computation is needed. Because rDPUs are multiple bits wide (for instance, 32-bit), we talk about coarse-grained reconfigurability – in contrast to FPGAs with single-bit wide configurable logic blocks, called fine-gained reconfigurable.
rDPAs are structurally programmed from “config-ware” source code , compiled into pipe-networks to be mapped onto the rDPA. rDPAs are not-stream-driven and have no fetch at run time statement. rDPUs do not have a program counter. 
- ^ Jump up to:a b Field-Programmable Logic: Architectures, Synthesis and Applications Reiner W. Hartenstein, Springer Science & Business Media, 24-Aug-1994
- ^ Jump up to:a b c d e f g h Compilation Techniques for Reconfigurable Architectures , Springer Science & Business Media, 02-Apr-2011
- Jump up^ Designing Embedded Processors: A Low Power Perspective, Springer Science & Business Media, 27-Jul-2007
- Jump up^ Reconfigurable System Design and Verification, CRC Press, 17-Feb-2009