Processor register

In computer architecture , a processor register is quickly accessible to a computer central processing unit (CPU). Registers usually consist of a small amount of fast storage , but some registers have specific hardware functions, and may be read-only or write-only. Registers are typically addressed by mechanisms other than hand-held , but may be assigned to memory address eg DEC PDP-10 , ICT 1900 .

Almost all computers, whether load / store architecture or not, load data from a larger memory where it is used for arithmetic operations and is manipulated or tested by machine instructions . Manipulated data is then often stored back to main memory, by the same instruction or by a subsequent one. Modern processors use static or dynamic RAM as main memory, with the latter usually accessed via one or more cache levels .

Processor registers are normally at the top of the memory hierarchy , and provide the fastest way to access data. The term normally refers to the group of registers that are directly encoded as part of an instruction, as defined by the statement set . However, modern high-performance CPUs often have duplicates of these “architectural registers” in order to improve performance through registering renaming , allowing parallel and speculative execution . Modern x86 design developed these techniques around 1995 with the release of Pentium Pro , Cyrix 6×86 , Nx586 , and AMD K5 .

A common property of computer programs is locality of reference , which refers to accessing the same values ​​repeatedly and holding frequently used values ​​in registers to improve performance; this makes fast registers and caches meaningful. [1] Allocating frequently used variables to registers can be critical to a program’s performance; This register is being compiled in the code generation phase, or manually by an assembly language program.

Categories of registers

Registers are actually measured by the number of bits they can hold, for example, an ” 8-bit register” or a ” 32-bit register”. A processor often contains several types of registers, which can be classified according to their

  • User-accessible registers can be read or written by machine instructions. The most common division of the user-accessible registers.
    • Data registers can hold numeric values ​​such as integer and, in some architectures, floating-point values, as well as characters , small bit arrays and other data. In some older and lower end CPUs, a special data register, known as the accumulator , is used implicitly for many operations.
    • Address registers hold addresses and are used by instructions That Indirectly access primary memory .
      • Some processors contain registers that can only be used to hold an address to hold a number of values ​​(in some cases used as an index register whose value is added as an offset from some address); others allow registers to hold. A wide variety of possible addressing modes , used to specify the effective address of an operand, exist.
      • The stack is used to manage the run-time stack . Rarely, other data stacks are addressed by dedicated address registers, see stack machine .
    • General-purpose registers ( GPR s) can blind Both data and addresses, ie, They Are combined data / address registers and Rarely the register file is unified to include floating point as well.
    • Status registers hold truth values often used to determine whether or not they should be executed.
    • Floating-point register s ( FPR s) floating point store numbers in many architectures.
    • Constant registers hold read-only values ​​such as zero, one, or pi .
    • Vector registers hold data for vector processing done by SIMD instructions (Single Instruction, Multiple Data).
    • Special-purpose registers ( SPR ) hold program state; they usually include the counter program , also called the pointer statement, and the status register ; the program counter and status register may be combined with a program status word (PSW) register. The above mentioned stack is sometimes included in this group. Embedded microprocessors can also have corresponding registers for specialized hardware elements.
    • In some architectures, model-specific registers (also called machine-specific registers ) Because their meanings are attached to the design of a specific processor, they can not be expected to remain standard between processor generations.
    • Memory Type Range Registers ( MTRR s)
  • Internal registers – not accessible by instructions, used internally for processor operations.
    • Register statement , holding the statement currently being executed.
    • Registers related to fetching information from RAM , a collection of storage registers located on separate chips from the CPU:
      • Memory buffer register ( MBR )
      • Memory data register ( MDR )
      • Memory address register ( MAR )
  • Architectural register– The registers visible to software defined by an architecture may not correspond to the physical hardware, if there is register renaming being performed by the underlying hardware.

Hardware registers are similar, but occur outside CPUs.

In some architectures (such as SPARC and MIPS ), the first or the last register in the integer register file is a pseudo-register in a way that it is hardwired to always return when it reads (mostly to simplify indexing modes), and it can not be overwritten. In Alpha this is also done for the floating-point register file. As a result of this, register files are commonly quoted as having one register; for example, 32 registers are quoted when only 31 of them fit within the above definition of a register.


The following table shows the number of registers in several mainstream architectures. Note that in x86-compatible processors the stack pointer ( ESP ) is an integer register, even though there is a limited number of instructions that can be used to operate on its contents. Similar caveats apply to most architectures.

ALTHOUGH all of the above listed architectures are different, Almost all are a basic arrangement Known as the Von Neumann architecture , first Proposed by the Hungarian-American mathematician John von Neumann . It is also noteworthy that the number of registers on GPUs is much higher than that on CPUs. [1] [2]

Architecture GPRs / data + address registers FP
AT & T Hobbit 0 stack of 7 The AT & T Hobbit ATT92010 (around 1992) was a commercial version of the 32-bit CRISP (stack machine) processor with RISC style instruction, inspired by the Bell Labs C Machine project, aimed at a design optimized for the C language, Hobbit has no global registers. Addresses can be direct or indirect memory (for pointers) relative to the stack without extra instructions or operand bits. The cache is not optimized for multiprocessors and is customizable with ASIC design in IEEE standard. [3]
Cray-1 [4] 8 scalar data, 8 addresses 8 scalar, 8 vector (64 elements) Scalar data registers can be integer or floating-point; also 64 scalar scratch pad T registers and 64 address scratch pad B registers
4004 [5] 1 accumulator, 16 others 0 Register A is for general purpose, while r0-r15 are registered for the address and segment.
8008 [6] 1 accumulator, 6 others 0 The A register is an accumulator to which all arithmetic is done; the H and L registers can be used in combination as an address register; all registers can be used as operands in load / store / move / increment / decrement instructions and the other operand in arithmetic instructions. There is no FP unit available.
8080 [7] 1 accumulator, 6 others 0 More a stack pointer. The A register is an accumulator to which all arithmetic is done; the register peers B + C, D + E, and H + L, can be used as registers in some instructions; all registers can be used as operands in load / store / move / increment / decrement instructions and the other operand in arithmetic instructions. Some instructions only use H + L;another instruction swaps H + L and D + E. Floating point processors intended for the 8080 were Intel 8231 , AMD Am9511 and Intel 8232 . They were also easy to use with the Z80and similar processors.
iAPX432 0 stack of 6 The iAPX 432 was referred to as a micromainframe, designed to be fully implemented in high-level languages. The instruction set architecture was also entirely new and significant from Intel’s previous 8008 and 8080 processors as the iAPX 432 programming model was a stack machine with no visible general-purpose registers. It is more commonly used in hardware and microcode. Direct support for various data structures has also been
16-bit x86 [8] 8 stack of 8 (if FP present) 8086 / 8088 , 80186 / 80188 , 80286 , with 8087 , 80187 or 80287 for floating-point, with an 80-bit wide, 8 deep stack register With Some instructions to use reliable registers relative to the top of the stack as operands; without 8087/80187/80287, no floating-point registers
IA-32 [9] 8 stack of 8 (if FP present), 8 (if SSE / MMX present) 80386 required 80387 for floating-point, with floating point, with both having an 80-bit wide, 8 deep register stack with some instructions. The Pentium III and later had the SSE with additional 128-bit XMM registers.
x86-64 [9] [10] 16 32 FP registers are 128-bit XMM registers, later extended to 256-bit YMM registers with AVX / AVX2 and 512-bit ZMM0-ZMM31 registers with AVX-512 . [11]
Xeon Phi [12] 16 32 Including 32 256/512-bit ZMM registers with AVX-512.
Geode GX 1 data, 1 address 8 Geode GX / GX Media / 4×86 / 5×86 is the emulation of 486 / Pentium compatible processor made by Cyrix / National Semiconductor . Like Transmeta , the processor had a translation that translated into a code and executed it. citation needed ] It does not support 128-bit SSE registers, just the 80387 stack of eight 80-bit floating point registers, and partially supporting 3DNow!from AMD. The native processor only contains 1 data and 1 address register for all purposes and 4 paths of 32-bit naming register r1 (base), r2 (data), r3 (back pointer), and r4 (stack pointer) within scratchpad sram for L1 cache for x86 code emulation (note that it’s not compatible with some 286/386/486 instructions in real mode).citation needed ] AMD acquired from National Semiconductor and branded with Athlon core in embedded market.
SunPlus SPG 0 6 A 16-bit wide, 32-bit address space stack machine processor made from Taiwanese semiconductor called “Sunplus”, it can be found on Vtech’s v’mile line for educational purposes and video game console like Mattel hyperscan, XaviXPORT. Floating Point Unit has 80-bit 6 stage stack.
VM Labs Nuon 0 1 a 32-bit stack machine that developed by VM Labs for specialized multimedia purpose. It can be found on the company’s own Nuon DVD player console line and Game Wave Family Entertainment System from ZaPit games. The design was heavy influence by Intel’s MMX technology, it is contained in 128 bytes unified stack cache for both vector and scalar instructions. the 32-bit 32 bit 32bit SIMD scalar register through bank renaming, no integer register found in this architecture.
Nios II [13] [14] 31 8 Nios II is based on MIPS IV instruction set citation needed ] and has 31 32-bit GPRs, with register 0 being hardwired to zero and 64-bit floating point registers citation needed ]
Motorola 6800 [15] 2 data, 1 index 0 More a stack pointer
Motorola 68k [16] 8 data (d0-d7), 8 addresses (a0-a7) 8 (if FP present) Address register 8 (a7) is the stack pointer. 68000, 68010, 68012, 68020, and 68030 require an FPU for floating point; 68040 had FPU built in. FP registers are 80-bit.
SH 16-bit 1 6
Emotion Engine 32 32 SIMD + 32 Vector The Emotion Engine’s core contains 32-bit 32-bit general-purpose registers for integer computation and 32-bit 128-bit SIMD registers for storing SIMD instruction, streaming data value and some integer calculation value. one accumulator register for connecting general floating-point computation to vector register file on co-processor. The coprocessor is built via 32 entries 128-bit vector register file (can only store vector value that pass from accumulator in cpu.) And no integer register is built in. Both vector co-processor (VPU 0/1) and emotion engine are built on the MIPS instructions set. Accumulator in this case is not general purpose but control status.
CUDA 1 8/16/32/64/128 Each CUDA core contains a single 32/64-bit integer data register while the floating point unit contains a much larger number of registers:

  • the Tesla 1.0 -based G8x contains 8 × 128-bit HDR vector registers,
  • the Tesla 2.0 -based GT200 increased the count to 16 × 128-bit
  • Fermi extended the register width to 256 bits and increased the register count to 32, (32 × 256-bit)
  • Kepler increased it to 64. (64 × 256-bit)
  • Maxwell contains a massive amount of 128,512-bit vector registers. (128 × 512-bit)
  • Pascal 😕
  • Volta 😕 quote needed ]
IBM / 360 16 4 (if FP present) This applies to S / 360’s successors, System / 370 through System / 390 ; FP was optional in System / 360, and always present in S / 370 and later. In processors with the Vector Facility, there are 16 vector registers containing a machine-dependent number of 32-bit elements. [17]
z / Architecture 16 16 64-bit version of S / 360 and successors
MMIX [18] 256 256 An instruction set designed by Donald Knuth in the late 1990s for pedagogical purposes.
NS320xx [19] 8 8 (if FP present)
Xelerated X10 1 32 has a 32/40 bit stack machine based network with MIPS instruction and 128 bit floating point unit.
Parallax Propeller 0 2 An eight core 8/16 bit sliced ​​stack machine controller with a single logic circus inside, have eight cog counter (core) and each contain three 8/16 bit special control registers with 32 bit x 512 ram stack however it does not carry any general register for integer purpose. unlike most of the above, in which case they may be accessed in the same way. Floating point unit is external and it contains two 80 bit vector register.
Itanium 128 128 And 64 1-bit predicate registers and 8 branch registers. The FP registers are 82-bit.
SPARC 31 32 Global register 0 is hardwired to 0. Uses register windows .
IBM POWER 32 32 And 1 link and 1 count register.
Power Architecture 32 32 And 1 link and 1 count register. Processors supporting the Vector facility also have 32 128-bit vector registers,
Blackfin 8 16 containing two external 40 bit accumulator, but no are general purpose. Support 64 bit RISC ISA architecture, vector register are 256 bit.
IBM Cell SPE 128 128 GPRs, which can hold integer, address, or floating-point values [20]
PDP-10 16 0 All may be used (integer, float, stack pointer, jump, indexing, etc.). Every 36-bit memory (or register) can also be manipulated as a half-word, which can be considered an (18-bit) address. Other words are used by certain instructions. In the original PDP-10 processors, these 16 GPRs also corresponded to main (ie core ) memory locations 0-15; a hardware option called “fast memory” implemented the registers as separate ICs, and references to memory locations 0-15 referred to the IC registers. Later models implemented the registers as “fast memory” and continued to make memory locations 0-15 refer to them. Movement instructions take (register, memory) operands: MOVE 1,2is register-register, and MOVE 1,1000is memory-to-register.
PDP-11 8 0 R7 is actually the Program Counter. Any register can be a stack pointer but R6 is used for hardware interrupts and traps.
VAX 16 0 Three of the registers have special uses: R12 (Argument Pointer), R13 (Frame Pointer), and R14 (Stack Pointer), while R15 refers to the Program Counter.
Alpha 31 31 Registers R31 (integer) and F31 (floating-point) are hardwired to zero.
6502 1 data, 2 index 0 6502’s content A (Accumulator), X, Y are indirect and direct index registers (respectively) and SP register are specific index only.
W65C816S 1 0 65C816 is the 16-bit successor of the 6502. X, Y, and D (Direct Page register). main accumulator extended to 16-bit (B) while keep 8-bit (A) for 24-bit (16-bit wide data instruction / 24-bit memory address).
65k 1 0 Direct successor of 6502, 65002 only content A (Accumulator) 32-bit and 64-bit instruction wide, support 48-bit virtual address in software mode, X, Y are still condition register and remain 8-bit and SP register are specific index but increase to 16-bit wide.
Me p 4 8 Media-embedded processor was a 32 bit processor developed by Toshiba, a modded 8080 instruction set with only A, B, C, D register available through all mode (8/16/32 bit) and incompatible with x86, however it contains 80 bit floating point unit that is x87 compatible.
PIC microcontroller 1 0
AVR microcontroller 32 0
ARM 32-bit (ARM / A32, Thumb / T32) 14 Varies (up to 32) r15 is the program counter, and not usable as a GPR; r13 is the stack pointer; r8-r13 can be switched out for others (banked) on a processor mode switch. Older versions had 26-bit addressing, [21] and used upper bits of the counter program (r15) for status flags, making that register 32-bit.
ARM 64-bit (A64) [22] 31 32 Register r31 is the stack pointer or hardwired to 0, depending on the context.
MIPS 31 32 Register 0 is hardwired to 0.
Epiphany 64 (per core) [23] Each instruction may be interpreted as an integer or a single precision floating point. Architecture is scalable to 4096 cores with 16 and 64 core implementations currently available.

Register use

The number of registers was available processor and the Operations That Can Be Performed using Those registers: has a significant impact on the efficiency of code generated by Optimizing compilers . The Strahler number of an expression tree gives the minimum number of registers required to evaluate that expression tree.

See also

  • CPU cache
  • Register allocation
  • Register file
  • Shift register


  1. ^ Jump up to:b “A Survey of Techniques for Designing and Managing CPU Register File”. Concurrency and Computation . Wiley. 2016. doi : 10.1002 / cpe.3906 .
  2. Jump up^ “A Survey of Techniques for Architecting and Managing GPU Register File”, IEEE TPDS, 2016
  3. Jump up^ “great microprocessor of the past and present” . cpushock . April 2006.
  4. Jump up^ “Cray-1 Computer System Hardware Reference Manual” (PDF) . Cray Research . November 1977.
  5. Jump up^ “MCS-4 Micro Computer Set Users Manual” (PDF) . Intel. February 1973.
  6. Jump up^ “8008 8 Parallel Central Processor Unit Users Manual” (PDF) . Intel. November 1973 . Retrieved January 23, 2014 .
  7. Jump up^ “Intel 8080 Microcomputer Systems User’s Manual” (PDF) . Intel. September 1975 . Retrieved January 23, 2014 .
  8. Jump up^ “80286 and 80287 Programmer’s Reference Manual” (PDF) . Intel. 1987.
  9. ^ Jump up to:b “Intel 64 and IA-32 Architectures Software Developer Manuals” . Intel.
  10. Jump up^ “AMD64 Programmer’s Manual Volume 1: Application Programming”(PDF) . AMD . October 2013.
  11. Jump up^ “Intel Architecture Set Extensions Instruction and Future Features Programming Reference” (PDF) . Intel . January 2018.
  12. Jump up^ “Intel Phi Xeon Coprocessor Instruction Set Architecture Reference Manual” (PDF) . Intel. September 7, 2012.
  13. Jump up^ “Nios Classic Processor Reference Guide” (PDF) . Altera . April 2, 2015.
  14. Jump up^ “Gen2 Nios II Processor Reference Guide” (PDF) . Altera. April 2, 2015.
  15. Jump up^ “M6800 Programming Reference Manual” (PDF) . Motorola . November 1976 . Retrieved May 18, 2015 .
  16. Jump up^ “Motorola M68000 Family Programmer’s Reference Manual” (PDF) . Motorola. 1992 . Retrieved June 13, 2015 .
  17. Jump up^ “IBM Enterprise Systems Architecture / 370 and System / 370 – Vector Operations” (PDF) . IBM . Retrieved January 5, 2014 .
  18. Jump up^ “MMIX Home Page” .
  19. Jump up^ “Series 32000 Databook” (PDF) . National Semiconductor .
  20. Jump up^ “Synergistic Processor Unit Instruction Set Architecture Version 1.2″(PDF) . IBM. January 27, 2007.
  21. Jump up^ “Call Procedure Standard for the ARM Architecture” (PDF) . ARM Holdings . November 30, 2013 . Retrieved 27 May 2013 .
  22. Jump up^ “Standard Call Procedure for the ARM 64-bit Architecture” (PDF) . ARM Holdings. May 22, 2013 . Retrieved 27 May 2013 .
  23. Jump up^ “Epiphany Architecture Reference” (PDF) .

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