Princeton Application Repository for Shared-Memory Computers

Princeton Application Repository for Shared-Memory Computers (PARSEC) is a benchmark suite of multi-threaded emerging workloads that is used to evaluate and develop next-generation chip-multiprocessors . It was collaboratively created by Intel and Princeton University to drive research efforts on future computer systems. [1] [2] Since its inception the benchmark continues to be improved by a wide range of research institutions. [3] PARSEC is available and is used for both academic and non-academic research. [4] [5] [6]


With the emergence of chip-multiprocessors: The new technology caused a disruptive change. [2] [7] For the first time in computer history software, it is possible to use the following information in order to: computer systems. At that time parallel software only existed in very specialized areas. However, before chip-multiprocessors were widely available software developers were not willing to rewriteany mainstream programs, which means hardware manufacturers. This is a problem that is more likely to be of a different nature than that of benchmarking.

PARSEC was created to break this circular dependency. It was designed to fulfill the following objectives [8]

  1. Focuses on multithreaded apps
  2. Includes emerging workloads
  3. Has a diverse selection of programs
  4. Workloads employ state-of-art techniques
  5. The suite supports research

Traditional benchmarks that are publicly available before PARSEC are generally limited to unparallelized, serial version. Parallel programs were only prevalent in the field of High-Performance Computing and have a much smaller scale in business environments. [9] Chip-multiprocessors, however, have been widely expected to be used in parallel computing.


The PARSEC Benchmark Suite is available in version 2.1, which includes the following workloads: [10]

  • Black-Scholes
  • Bodytrack
  • Canneal
  • dedup
  • Facesim
  • tag
  • Fluidanimate
  • Freqmine
  • raytrace
  • Streamcluster
  • swaptions
  • Vips
  • X264


  1. Jump up^ “Intel Teams with Universities on Multicore Software Suite” . EDN . Retrieved 2006-08-22 .
  2. ^ Jump up to:b “Designing future computers with future workloads” . Research @ Intel . Retrieved 2008-02-26 .
  3. Jump up^ “Intel CTO looks into the future: Measuring the value and need for multi-core” . Gabe on EDA . Retrieved 2006-08-31 .
  4. Jump up^ “The PARSEC Benchmark Suite” . Princeton University . Retrieved 2008-01-05 .
  5. Jump up^ Bhadauria, Major; Weaver, Vincent M .; McKee, Sally A. (October 2009), “Understanding Performance PARSEC on Contemporary PMCs” , Proceedings of the 2009 IEEE International Symposium on Workload Characterization , IEEE
  6. Jump up^ Barrow-Williams, Nick; Fensch, Christian; Moore, Simon (October 2009), “A Characterization of Communication and PARSEC SPLASH-2” , Proceedings of the 2009 IEEE International Symposium on Workload Characterization , IEEE
  7. Jump up^ Rabaey, Jan M .; Burke, Daniel; Lutz, Ken; Wawrzynek, John (July-August 2008), “Workloads of the Future” (PDF) , IEEE Design & Test of Computers , IEEE
  8. Jump up^ Bienia, Christian; Kumar, Sanjeev; Singh, Jaswinder Pal; Li Kai (October 2008), “The PARSEC Benchmark Suite: Characterization and Architectural Implications” , Proceedings of the 17th international conference is Parallel architectures and technical compilation , Association for Computing Machinery, New York, NY, USA
  9. Jump up^ Bienia, C .; Kumar, S .; Kai Li (2008). “PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors”. 2008 IEEE International Symposium on Workload Characterization . p. 47. doi : 10.1109 / IISWC.2008.4636090 . ISBN  978-1-4244-2777-2 .
  10. Jump up^ Bienia, Christian; Li Kai (June 2009), “PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors” , Proceedings of the 5th Annual Workshop on Modeling and Simulation Benchmarking , Association for Computing Machinery, New York, NY, USA

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