Memory dependence prediction

Memory dependence prediction is a technique employed by high-performance out-of-order execution microprocessors That execute memory access operations (loads and stores) out of program order, to predict true dependencies entre loads and stores at instruction execution time. With the predicted dependence information, the processor can then decide to speculatively execute certain loads and stores out of order, while preventing other loads and out-of-order (keeping them in-order). Later in the pipeline , memory disambiguation techniques are used to determine if and how to recover.

By using the memory dependence predictor to keep most of the loadings of the processor, the processor gains the benefits of aggressive operations. This increases performance because it reduces the number of pipeline flushes that are required to recover from these memory dependence violations. See the memory disambiguation article for more information on memory dependencies, memory dependence violations, and recovery.

In general, memory dependence is predicted that they are dependent on the same memory location. In addition to store to load (RAW or true) memory dependence prediction for the out-of-order scheduling of loads and blinds, other applications of memory dependence prediction have been proposed. See for example. [1]

Memory dependence prediction is an optimization on top of memory dependence speculation. Sequential execution semantics imply that stores and tasks appear in the order specified by the program. However, it may be possible to execute two different operations in a different program. This is possible when the two operations are independent. In memory dependence speculation a load may be allowed to execute before a store that precedes it. Speculation succeeds when the load is independent of the store, that is, when the two instructions access different memory locations. Speculation fails when the load is dependent upon the store, which is when the two accesses overlap in memory. In the first, modern out-of-order designs, memory speculation was not used as its benefits were limited. The the the the the,,,,,,,,,,,,,,,,,. innaive memory dependence speculation , [2] a load is allowed to bypass any preceding store. As with any form of speculation, it is important to weigh the benefits of correct speculation against the penalty paid on incorrect speculation. As the scope of out-of-order performance increases, the performance benefits of naive speculation decrease. To retain the benefits of aggressive memory speculation while avoiding the costs of mispeculation several predictors have been proposed.

Selective memory dependence prediction [2] [3] stalls specific loads until it is certain that no violation may occur. It does not explicitly predict dependencies. This predictor may result in suboptimal performance. In fact, in some cases it is possible that it can not be better than possible. This is the reason why it is so much easier to execute. Exact memory dependence prediction was developed at the University of Wisconsin-Madison. Specifically, Dynamic Speculation and Synchronization [2] [3]It should not be necessary to wait until it is necessary. This predictor predicts exact dependencies (store and load pair). The synonym predictor [1] groups together all dependences that share a common load or store instruction. The store sets [4] predictor represents multiple potential dependencies by all possible blinds The store barrier [5]predictor treats certain store instructions as barriers. That is, all subsequent load or store operations are not allowed to bypass the specific store. The store barrier predictor does not explicitly predict dependencies. This predictor may unnecessarily delay subsequent, yet independent loads. Memory dependence prediction has other applications beyond the scheduling of loads and stores. For example, speculative memory cloaking [1] and speculative memory bypassing [1] use memory dependence prediction to streamline the communication of values ​​through memory.

Analogy to branch prediction

Memory dependence prediction for loads and stores is analogous to branch prediction for conditional branch instructions. In branch prediction, the branch predictor predicts which way the branch will be known. The processor can then speculatively fetch and execute instructions on one of the paths of the branch. Later, when the statement executes, it can be determined if the branch statement was correctly predicted. If not, this is a misprediction , and a pipeline is necessary to throw away instructions that have been speculatively fetched and executed.

Branch prediction can be thought of as a two step process. First, the predictor determines the direction of the branch (taken or not). This is a binary decision. Then, the predictor determines the actual target address. Similarly, memory dependence prediction can be thought of as a two step process. First, the predictor determines whether there is a dependence. Then it determines which this dependence is.

See also

  • Memory-level parallelism
  • Memory disambiguation


  1. ^ Jump up to:d Streamlining Operation Inter-Communication via Memory Memory Dependence Prediction, Moshovos and Sohi, in the Proceedings of the Annual ACM / IEEE International Symposium on Microarchitecture, Dec. 1997.
  2. ^ Jump up to:c Dynamic Speculation and Synchronization of Memory Dependencies, Moshovos, Breach, Vijaykumar and Sohi, in the Proceedings of the 24th Annual ACM / IEEE Conference on Computer Architecture, June 1997. Also as technical report, Computer Sciences Department , University of Wisconsin-Madison, March 1996.
  3. ^ Jump up to:b Memory Dependence Prediction, Moshovos, Ph.D. Thesis, Computer Sciences Department, University of Wisconsin-Madison, Dec. 1998.
  4. Jump up^ Memory Dependence Prediction Using Store Sets, Chrysos and Emer, in the Proceedings of the 25th Annual ACM / IEEE Conference on Computer Architecture, June 1998.
  5. Jump up^ Apparatus to dynamically control the out-of-order execution of load-store instructions in a single processor, Hesson, LeBlanc and Ciavaglia 1997.

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