Superscalar processor

processor is a processor that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor That can execute at MOST one single instruction per clock cycle, a superscalar processor can execute more than one instruction During a clock cycle by Simultaneously multiple dispatching instructions to different execution units on the processor. It therefore Allows for more throughput (the number of instructions That Can Be Executed in a unit of time) than Otherwise Would be feasible at a Given clock rate. Each execution unit is not a separate processor (or a core if the processor is a multi-core processor ), but an execution resource within a single CPU such as an arithmetic logic unit .

In Flynn’s taxonomy , a single-core superscalar processor is classified as an SISD processor (Single Instruction stream, Single Data stream), although many superscalar processors support short operations and can be classified as Single Instruction Stream ( SIMD ) . A multi-core superscalar processor is classified as an MIMD processor (Multiple Instruction streams, Multiple Data streams).

While a superscalar CPU is typically also pipelined , superscalar and pipelining performance are considered different performance enhancement techniques. The multiple executions of multiple executions in parallel by multiple execution of multiple executions.

The superscalar technique is traditionally associated with several identifying characteristics (within a given CPU):

  • Instructions are issued from a sequential stream statement
  • The CPU dynamically checks for data at run time (versus software checking at compile time )
  • The CPU can execute multiple instructions per clock cycle

History

Seymour Cray ‘s CDC 6600 from 1966 is Often MENTIONED as the first superscalar design. The 1967 IBM System 360 Model 91 was another superscalar mainframe. The Motorola MC88100 (1988), the Intel i960 CA (1989) and the AMD 29000 -series 29050 (1990) microprocessors were the first commercial single-chip superscalar microprocessors. RISC microprocessors like these were the first to have superscalar execution, because RISC architectures frees transistors and die areas that could be used to include multiple execution units (this was why RISC designs were faster than CISC designs through the 1980s and into the 1990s).

Except for CPUs used in low-power applications, embedded systems , and battery- powered devices, essentially all-purpose CPUs are since superscalar.

The P5 Pentium was the first superscalar x86 processor; the Nx586 , P6 Pentium Pro and AMD K5 were among the first designs which decode x86 -instructions asynchronously into dynamic micro- microcode- like micro-opsequences to a microarchitecture superscalar ; this ouvert up for dynamic scheduling of buffered partial instructions and enabled more parallelism to be Extracted Compared to the more rigid methods used in the simpler P5 Pentium ; it also simplified speculative executionand higher clock frequencies compared to designs such as the advanced Cyrix 6×86 .

Scalar to superscalar

The simplest processors are scalar processors . Each instruction executed by a scalar processor typically manipulates one or two data items at a time. By contrast, each statement executed by a vector processor operates simultaneously on many data items. An analogy is the difference between scalar and vector arithmetic. A superscalar processor is a mixture of the two. Each instruction processes one data item, but there are multiple execution units within each CPU.

Superscalar CPU design emphasizes improving the accuracy and accuracy of the process. This has become increasingly important as the number of units has increased. While early superscalar CPUs would have two ALUs and a single FPU , a modern design such as the PowerPC 970 includes oven ALUs, two FPUs, and two SIMD units. If the dispatcher is ineffective at keeping track of instructions, the performance of the system will be less than that of a simpler, cheaper design.

A superscalar processor usually has an execution rate in excess of one instruction per cycle machine . But simply processing multiple instructions concurrently does not make an architecture superscalar, since pipelined , multiprocessor or multi-core architectures also achieve that, but with different methods.

In a superscalar CPU the dispatcher reads instructions from memory and which ones can be run in parallel, dispatching each one of the several execution units contained inside a single CPU. Therefore, a superscalar processor can be envisioned having multiple parallel pipelines, each of which is processing instructions simultaneously from a single instruction thread.

Limitations

Available performance improvement from superscalar techniques is limited by three key areas:

  1. The degree of intrinsic parallelism in the instruction stream (instructions requiring the same computational resources from the CPU).
  2. The complexity and time cost of dependency checking logic and register renaming circuitry
  3. The branch instruction processing.

Existing binary executable programs have varying degrees of intrinsic parallelism. In some cases instructions are not dependent on each other and can be executed simultaneously. In other cases they are inter-dependent: one statement impacts either resources or results of the other. The instructions a = b + c; d = e + fcan be run in parallel because none of the results depend on other calculations. However, the instructions may a = b + c; b = e + fnot be runnable in parallel, depending on the order in which the instructions are complete while they move through the units.

When the number of simultaneous statements increases, the cost of dependency checking increases rapidly. This is an error in the CPU’s clock rate. This cost includes additional logic gates required by the gates. Research citation needed ] shows the gate cost in some cases may be{\ displaystyle n ^ {k}} gates, and the delay cost {\ displaystyle k ^ {2} \ log n}where {\ displaystyle n} is the number of instructions in the processor’s instruction set, and {\ displaystyle k} is the number of

Even though the stream statement may contain no inter-instruction dependencies, a superscalar CPU must not be checked for that possibility, since there is no assurance otherwise and failure to detect a dependency would produce incorrect results.

No matter how advanced the semiconductor process or how fast the switching speed, this places has a practical limit. The process of controlling dependency grows rapidly, as it increases the complexity of the control of dependencies. Collectively the power consumption , the complexity and the gateway costs the achievable superscalar

However, even if given infinitely fast dependency checking logic on the principle of the superscalar CPU, if the statement itself has many dependencies, this would also limit the possible speedup. Thus the degree of intrinsic parallelism in the stream stream forms a second limitation.

Alternatives

Collectively, these limits drive investigation into alternative architectural changes such as very long word instruction (VLIW), explicitly parallel computing instruction (EPIC), simultaneous multithreading (SMT), and multi-core computing .

With VLIW, the burdensome task of dependency checking by hardware is removed and delegated to the compiler . Explicitly parallel computing instruction (EPIC) is like VLIW, with extra cache prefetching instructions.

Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of superscalar processors. SMT permits multiple independent threads of execution to be used by the modern processor architectures.

Superscalar processors Differ from multi-core processors in que la Several execution units arent Entire processors. A single processor is composed of finer-grained execution units such as the ALU , integer multiplier , integer shifter, FPU , etc. There may be multiple versions of each execution in parallel. This differs from a multi-core processor that competitively processes multiple threads, one thread per processing unit (called “core”). It also differs from a pipelined processor , where the multiple instructions can be concurrentlyassembly-line fashion.

The various alternative techniques are not mutually exclusive-they can be combined in a single processor. Thus a multicore CPU is possible where each core is an independent processor containing multiple parallel pipelines, each pipeline being superscalar. Some processors also include vector capability.

See also

  • Out-of-order execution
  • Super-threading
  • Simultaneous multithreading (SMT)
  • Speculative execution / Eager execution
  • Software lockout , a multiprocessor issue similar to logic dependencies on superscalars
  • Shelving buffer

References

  • Mike Johnson , Superscalar Microprocessor Design , Prentice-Hall, 1991, ISBN  0-13-875634-1
  • Sorin Cotofana, Stamatis Vassiliadis, “On the Design Complexity of the Logic Issue of Superscalar Machines”, EUROMICRO 1998: 10277-10284
  • Steven McGeady , “The i960CA SuperScalar Implementation of the 80960 Architecture”, IEEE 1990, pp. 232-240
  • Steven McGeady , et al., “Performance Enhancements in the Superscalar i960MM Embedded Microprocessor,” ACM Proceedings of the 1991 Conference on Computer Architecture (Compcon) , 1991, p. 4-7

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