Stanford DASH

Stanford DASH was a coherent multiprocessor cache developed in the late 1980s by Anoop Gupta, John L. Hennessy , Mark Horowitz , and Monica S. Lam at Stanford University . [1] Stanford to up to 16 SGI IRIS 4D Power Series and Stanford-modified version of the Torus Routing Chip. [2] The boards designed at Stanford implemented a directory-based cache coherence protocol [3] allowing Stanford DASH to supportdistributed shared memory for up to 64 processors. Stanford DASH Was notable for aussi Both Supporting and helping to formalize weak memory consistency models , Including release consistency . [4] Because Stanford DASH Was the first operational machine-to include scalable Cache coherence, [5] it Influenced subsequent computer science research as well as the Commercially available SGI Origin 2000 . Stanford DASH is included in the 25th anniversary retrospective of selected papers from the International Symposium on Computer Architecture [6] and several computer science books, [7] [8] [9] [10] [11]has been simulated by the University of Edinburgh, [12] and is used as a case study in contemporary computer science classes. [13] [14]

References

  1. Jump up^ Lenoski, Daniel; Laudon, James; Gharachorloo, Kourosh; Weber, Wolf-Dietrich; Gupta, Anoop; Hennessy, John; Horowitz, Mark; Lam, Monica S. (1992). “The Stanford Dash Multiprocessor” . Computer . IEEE. 25 (3): 63-79. doi : 10.1109 / 2.121510 .
  2. Jump up^ Dally, William J .; Seitz, Charles L. (1986). “The torus routing chip”. Distributed Computing . Springer-Verlag. 1 (4): 187-196. doi : 10.1007 / BF01660031 .
  3. Jump up^ Lenoski, Daniel; Laudon, James; Gharachorloo, Kourosh; Gupta, Anoop; Hennessy, John (1990). “The directory-based cache coherence protocol for the multiprocessor DASH”. Proceedings of the 17th Annual International Symposium on Computer Architecture . ACM. pp. 148-159. doi : 10.1145 / 325164.325132 .
  4. Jump up^ Gharachorloo, Kourosh; Lenoski, Daniel; Laudon, James; Gibbons, Phillip; Gupta, Anoop; Hennessy, John (1990). “Memory consistency and event ordering in scalable shared-memory multiprocessors”. Proceedings of the 17th Annual International Symposium on Computer Architecture . pp. 15-26. doi : 10.1145 / 325096.325102 .
  5. Jump up^ Hennessy, John; Patterson, David (2003). Computer Architecture: A Quantitative Approach, (Third ed.). Morgan Kaufmann. p. 655. ISBN  1-558-60596-7 .
  6. Jump up^ Lenoski, Daniel; Laudon, James; Joe, Truman; Nakahira, David; Stevens, Luis; Gupta, Anoop; Hennessy, John (1998). “The DASH prototype: Implementation and Performance” . In Sohi, Gurindar. 25 years of the International Symposia on Computer Architecture (Selected Papers) . pp. 418-429.
  7. Jump up^ Suzuki, Norihisa (1992). Shared Memory Multiprocessing . The MIT Press. pp. 391-406. ISBN  0-262-19322-1 .
  8. Jump up^ Loshin, David (1994). High Performance Computing Demystified . Academic Press. pp. 80, 91. ISBN  0-124-55825-9 .
  9. Jump up^ Parhami, Behrooz (1999). Introduction to Parallel Processing: Algorithms and Architectures . Springer. pp. 450-451. ISBN  0-306-45970-1 .
  10. Jump up^ Hill, Mark; Jouppi, Norman; Sohi, Gurindar (2000). Readings in Computer Architecture . Morgan Kaufmann. pp. 583-599. ISBN  1-55860-539-8 .
  11. Jump up^ Dandamudi, Sivarama (2003). Hierarchical Scheduling in Parallel and Cluster Systems . Springer US. pp. 21-22. doi : 10.1007 / 978-1-4615-0133-6 .
  12. Jump up^ Institute for Computing Systems Architecture, School of Informatics, University of Edinburgh”Stanford DASH Architecture: Cluster Simulation Model”, Retrieved on 3 November 2015.
  13. Jump up^ Carl Olson and Mattan Erez, The University of Texas at Austin (2007)”The Stanford Dash Multiprocessor”, Retrieved on 3 November 2015.
  14. Jump up^ Meng Zhang, Duke University (2010)”The Stanford Dash Multiprocessor”, Retrieved on 3 November 2015.

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