A multi-core processor is a single computing component with two or more independent processing units called Expired cores, qui read and execute program instructions .  The instructions are ordinary CPU instructions (such as add, move data, and branch) but the single processor can run multiple instructions on separate cores at the same time, increasing overall speed for programs amenable to parallel computing .  Manufacturers Typically integrate the cores onto a single integrated system die (Known as a chip multiprocessor or CMP) or onto multiple dies in a single chip package.
A multi-core processor implements multiprocessing in a single physical package. Designers may couple cores in a multi-core device tightly gold loosely. For example, cores May or May not share caches , And They May Implement Message passing or shared-memory inter-core communication methods. Common network topologies to interconnect cores include bus , ring , two-dimensional mesh , and crossbar . Homogeneous multi-core systems include only identical cores; heterogeneous multi-core systems have not been identical (eg big.LITTLEhave the same instruction set, while AMD Accelerated Processing Units have not even share the same statement set). Just as with single-processor systems, cores in multi-core systems can implement such architectures as VLIW , superscalar , vector , or multithreading .
Multi-core processors are widely used across many application domains, including general-purpose , embedded , network , digital signal processing (DSP), and graphics (GPU).
The improvement in performance is the result of the use of a multi-core processor that depends on the software used and their implementation. In particular, possible gains are limited by the fraction of the software that can run parallel to multiple cores; this effect is described by Amdahl’s law . In the best case, so-called embarrassingly parallel problems may occur, or even more if the problem is split up within each core cache (s), avoiding use of much slower main-system memory . Most applications, however, are not accelerated so much unless programmers invest a prohibitive amount of effort in re-factoring the whole problem.  The parallelization of software is a significant ongoing topic of research.
The terms multi-core and dual-core most commonly refer to some of the central processing unit (CPU), but are also applied to digital signal processors (DSP) and system on a chip (SoC). The terms are used only to refer to multi-core microprocessors that are manufactured on the same integrated circuit die ; separate microprocessor dies in the same package, as such multi-chip module . This article uses the terms “multi-core” and “dual-core” for CPUs manufactured on the same integrated circuit, unless otherwise noted.
In contrast to multi-core systems, the multi-CPU term refers to a multiple-to-multiple-case separate-processing-units.
The terms many-core and massively multi-core are sometimes used to describe multi-core architectures with an especially high number of cores (tens or hundreds). 
Some systems use many soft microprocessors on a single FPGA . Each “core” can be considered a ” semiconductor intellectual property core ” as well as a CPU core. [ quote needed ]
While manufacturing technology improves, the size of individual gates, the physical limits of semiconductor -based microelectronics have become a major design concern. These physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance. Some instruction-level parallelism (ILP) methods Such As superscalar pipelining are suitable For Many applications are for others aim inefficient That Contain difficult-to-predict code. Many applications are better suited to thread-level parallelism(TLP) methods, and multiple independent CPUs are commonly used to increase a system’s overall TLP. A combination of increased available space and the demand for increased TLP led to the development of multi-core CPUs.
Several business motives drive the development of multi-core architectures. For decades, it has been possible to improve the performance of the integrated circuit (IC), which reduces the cost per device on the IC. Alternatively, for the same circuit area, more transistors could be used in the design, which increased functionality, especially for complex set computing instruction (CISC) architectures. Clock rates also increased by orders of magnitude in the late twentieth century, from several megahertz in the 1980s to several gigahertz in the early 2000s.
As the rate of clock speed increases slowed down, it is used in parallel computing in the form of multi-core processors. Multiple cores have been used on the same CPU chip, which could then be better than CPU chips with two or more cores. For example, Intel has produced a 48-core processor for cloud computing research; each core has an x86 architecture.  
Since they have been implemented in the past, they have implemented multiprocessing (SMP) designs using discrete CPUs.
- Using a proven processing-core design without architectural changes reduces design risk significantly.
- For general-purpose processors, much of the motivation for multi-core processors comes from Greatly diminished gains in processor performance from Increasing the operating frequency . This is due to three primary factors: 
- The memory wall ; the increasing gap between processor and memory speeds. This, in effect, pushes for cache sizes to be larger in order to mask the latency of memory. This helps only the extent that memory bandwidth is not bottleneck in performance.
- The ILP wall ; The increasing difficulty of finding a parallel to a single statement stream to keep a high-performance single-core processor busy.
- The power wall ; The growth of exponentially increasing power (exponentially increasing exponentially increasing heat) with each factorial increase of operating frequency. This increase can be mitigated by ” shrinking ” the processor by using smaller traces for the same logic. The power wall poses manufacturing, system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the wall and ILP wall .
In order to continue to deliver performance improvements for general-purpose processors, such as Intel and AMD have come to multi-core designs, sacrificing lower manufacturing-costs for higher performance in some applications and systems. Multi-core architectures are being developed, but so are the alternatives. An especially strong contender for established markets is the further integration of the peripheral functions into the chip.
The proximity of multiple CPU cores on the same die allows the cache coherency circuitry to operate at a much higher rate than is possible if the signals have to travel off-chip. Combining equivalent CPUs on a single platform improves the performance of cache snoop (alternative: Bus snooping ) operations. Put simply, this means clustering That signals entre different CPUs travel go short distances and therefore Those signals degrade less. These higher-quality signals allow more data to be felt in a given time period,
Multi-core CPU designs require much less printed circuit board (PCB) space than do multi-chip SMP designs. Also, a dual-core processor uses a single-core processors, principally because of the power required to drive signals external to the chip. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the front-side bus (FSB). In terms of competing technologies for the available silicon die area, multi-core design can make use of the CPU core library designs and produce a product with lower risk of design error than devising a new wider-core design. Also, adding more cache suffers from diminishing returns.
Multi-core chips also allow higher performance at lower energy. This can be a big factor in mobile devices that operate on batteries. Since each core in a multi-core CPU is more energy-efficient, the chip becomes more efficient than having a single large monolithic core. This allows higher performance with less energy. A challenge in this, however, is the additional overhead of writing parallel code. 
Maximizing the use of the computing resources provided by the multi-core processors requires adjustments to the operating system (OS) support and to existing application software. Also, the ability to multi-core processors to increase application performance depends on the use of multiple threads within applications.
Integration of a multi-core chip can lower the chip production yields. They are also more difficult to manage thermally than lower-density single-core designs. Intel has partially countered this first problem by creating its quad-core designs by combining two dual-core ones with a unified cache, hence any two working dual-core dies can be used, quad-core CPUs. From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence. Finally, raw processing power is not the only constraint on system performance. Two processing cores sharing the same system bus and memory bandwidth limits the real-world performance advantage. In a 2009 report, Dr Jun Ni, who’s been going to be a double-core guy, is giving up 30% to 70% improvement; if memory bandwidth is not a problem, then a 90% improvement can be expected; HOWEVER,Amdahl’s law makes this claim dubious.  It would be possible for an application that used two CPUs to end up running faster on a single-core one if communication between the CPUs was the limiting factor, which would count as more than 100% improvement.
The trend in processor development has been increasing ever since, as it has become possible.  In addition, multi-core chips mixed with simultaneous multithreading , memory-on-chip, and special-purpose “heterogeneous” (or asymmetric) cores promise further performance and efficiency gains,  especially in processing multimedia, recognition networking applications. For example, a big.LITTLE core includes a high-performance core (called ‘big’) and a low-power core (called ‘LITTLE’). There is also a trend towards improving energy-efficiency by focusing on performance-per-watt with advanced fine-grain gold ultra-fine grainpower management and dynamic voltage and frequency scaling (ie laptop computers and portable media players ).
Chips designed from the outset for a large number of cores (rather than having evolved from single core designs) are often referred to as manycore designs, emphasizing qualitative differences.
The composition and balance of the cores in multi-core architecture show great variety. Some architectures use one core design repeated consistently (“homogeneous”), while others use a mixture of different cores, each of which is optimized for a different, ” heterogeneous ” role.
The article “CPU designers debate multi-core future” by Rick Merritt, EE Times 2008,  includes these comments:
Chuck Moore […] suggests computers should be like cellphones, using a high-level programming interface.
[…] Atsushi Hasegawa, a senior chief engineer at Renesas , generally agreed. He suggests the cellphone’s use of many specialty cores working in concert is a good model for future multi-core designs.
[…] Anant Agarwal , founder and chief executive of Tilera , took the opposite view. He said multi-core chips need to be homogeneous collections of general-purpose cores to keep the software model simple.
An outdated version of an anti-virus application may create a new thread for a scan process, while its GUI threads waits for commands from the user (eg cancel the scan). In such cases, a multi-core architecture is one of the most important applications for the application of the single thread in the heavy lifting and the inability to balance the work evenly across multiple cores. Programming truly multithreaded code Often requires complex co-ordination of threads and can Easily Introduce subtle and difficult-to-find bugs due to the interweaving of processing on data shared entre threads (see thread-safety). Consequently, such code is much more difficult to debug than single-threaded code when it breaks. There has been a lack of motivation for writing consumer-level threaded applications because of the relative rarity of consumer-level demand for maximum use of computer hardware. Although one of the most important tools on the market, this one is one of the most important machines on the market. Also, serial tasks like decoding the entropy encoding algorithms used in video codecs are impossible to parallelize because each result is used to create the next result of the entropy decoding algorithm.
Given the increasing emphasis on multi-core chip design, the extent to which it can be increased the single greatest constraint on computer performance in the future. If developers are unable to provide a full range of services, then they will be able to reach an insurmountable performance ceiling.
The telecommunications market has been one of the first things in the world of data processing and has had a very rapid adoption of these multiple-core processors for the datapath and the control plane. These MPUs are going to replace  the traditional Network Processors that were based on proprietary microcode or picocode .
Parallel programming techniques can benefit from multiple cores directly. Some existing parallel programming models such as Cilk Plus , OpenMP , OpenHMPP , FastFlow , Skandium, MPI , and Erlang can be used on multi-core platforms. Intel introduced a new abstraction for C ++ parallelism called TBB . Other research efforts include the Codeplay Sieve System , Sun’s Fortress , Cray’s Chapel , and IBM’s X10 .
Multi-core processing has also affected the ability of modern computational software development. Developers programming in newer languages might find that their modern languages do not support multi-core functionality. This then requires the use of numerical libraries to access code written in languages like C and Fortran , which perform math computations faster than newer languages like C # . Intel’s MKL and AMD’s ACMLare written in these languages and take advantage of multi-core processing. Balancing the application workload can be problematic, especially if they have different performance characteristics. There are different conceptual models for dealing with the problem, for example using the coordination language and the program building blocks (programming libraries or higher-order functions). Each block can have a different native implementation for each processor type. Users simply program using these abstractions and an intelligent compiler chooses the best implementation based on the context. 
Managing concurrency acquires a central role in developing parallel applications. The basic steps in designing parallel applications are:
- The partitioning stage of a design is intended to expose opportunities for parallel execution. Hence, the focus is on defining a large number of small tasks in order to yield that is a fine-grained decomposition of a problem.
- The tasks are created by a competitor but not in general, independently. The computation to be performed in one task. Data must then be transferred between tasks so as to allow computation to proceed. This information is specified in the communication phase of a design.
- In the third stage, development moves from the abstract to the concrete. Developers revisit decisions made in the partitioning and communication phases. In particular, it is useful to combine, or agglomerate, tasks identified by the partitioning phase, so to provide a smaller number of tasks, each of greater size. They also determine whether it is worthwhile to replicate data and computation.
- In the fourth and final stage of the design of parallel algorithms, the developers specify where each task is to execute. This mapping problem does not occur on uniprocessors or on shared-memory computers that provide automatic task scheduling.
On the other hand, on the server side , multi-core processors are ideal because they allow many users to connect to a site simultaneously and have independent threads of execution. This allows for Web servers and application servers that have much better throughput .
Vendors may license some software “per processor”. This can give rise to ambiguity, because a “processor” may consist of a single core or a combination of cores.
- INITIALLY, Reviews some of ict for enterprise software, Microsoft continued to use a per- socket licensing system. However, for some software such as BizTalk Server 2013 , SQL Server 2014 , and Windows Server 2016 , Microsoft has shifted to per-core licensing. 
- Oracle Corporation counts an AMD X2 or an Intel dual-core CPU as a single processor [ citation needed ] but uses other metrics for other types, especially for processors with more than two cores. 
Embedded computing operates in an area of distinct processor technology from that of “mainstream” PCs. The same way towards multi-core apply here too. Indeed, in many cases the application is a “natural” fit for multi-core technologies, if the task can easily be partitioned between different processors.
In addition, embedded software is produced for the purpose of a specific hardware release, making software portability , legacy code or supporting independent developers. As a result, it is easier for developers to adopt new technologies and has resulted in a greater variety of multi-core processing architectures and suppliers.
As of 2010 , multi-core network processing devices have become mainstream, with companies such as Freescale Semiconductor , Cavium Networks , Wintegra and Broadcom all manufacturing products with eight processors. For the system developer, SMP operating system. SMP operating system. To address this issue, companies such as 6WIND provide portable packet processing software designed so that the networking data plane runs in a fast path environment outside the OS. 
In digital signal processing la même trend Applies: Texas Instruments Has the three-core TMS320C6488 and TMS320C5441 oven-core, Freescale the four-core MSC8144 and MSC8156 six-core (and They Are Both Stated-have working one eight-core Successors). Newer entries include the Storm-1 family from Stream Processors, Inc. with 40 and 80 general purpose ALUs per chip, all programmable in SIMD engine and Picochip with three-hundred processors on a single die, focused on communication applications.
As of 2016 heterogeneous multi-core solutions are becoming more common: Xilinx Zynq UltraScale + MPSoC has quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5. Software solutions such as OpenAMP are used to help with inter processor communication.
- Adapteva Epiphany, has many-core processor architecture which allows up to 4096 on-chip processors, but only has 16 core version has been commercially produced.
- Aeroflex Gaisler LEON3 , has multi-core SPARC that also exists in a fault-tolerant version .
- Ageia PhysX , a multi-core physics processing unit .
- Ambric Am2045, 336-core Massively Parallel Processor Array (MPPA)
- A-Series , dual-, triple-, and quad-core Accelerated Processor Units (APU).
- Athlon 64 , Athlon 64 FX and Athlon 64 X2 family, dual-core desktop processors.
- Athlon II , dual-, triple-, and quad-core desktop processors.
- FX-Series , quad-, 6-, and 8-core desktop processors.
- Opteron , dual-, quad-, 6-, 8-, 12-, and 16-core server / workstation processors.
- Phenom , dual-, triple-, and quad-core processors.
- Phenom II , dual-, triple-, quad-, and 6-core desktop processors.
- Sempron X2 , dual-core entry level processors.
- Turion 64 X2 , dual-core laptop processors.
- Ryzen , quad-, 6-, 8-, 12-, and 16-core desktop processors
- Epyc , 8-, 16-, 24-, and 32-core server processors
- Multi-core Radeon and FireStream GPU / GPGPU (10 cores, 16 5-way wide superscalar stream processors per core)
- Analog Devices Blackfin BF561, a symmetrical dual-core processor
- ARM MPCore is a fully synthesizable multi-core container for ARM11 MPCore and ARM Cortex-A9 MPCore processor cores, designed for high-performance embedded and entertainment applications.
- ASOCS ModemX, up to 128 cores, wireless applications.
- Azul Systems
- Vega 1, a 24-core processor, released in 2005.
- Vega 2, a 48-core processor, released in 2006.
- Vega 3, has 54-core processor, released in 2008.
- Broadcom SiByte SB1250, SB1255, SB1455; BCM 2836 quad-core ARM SoC (designed for the Raspberry Pi 2)
- CSX700, 192-core processor, released in 2008 (32/64-bit floating point, Integer ALU)
- Cradle Technologies CT3400 and CT3600, both multi-core DSPs.
- Cavium Networks Octeon, has 32-core MIPS MPU .
- Coherent Logix hx3100 Processor , a 100-core DSP / GPP processor
- Freescale Semiconductor QorIQ series processors, up to 8 cores, Power Architecture MPU .
- Hewlett-Packard PA-8800 and PA-8900 , dual core PA-RISC processors.
- POWER4 , a dual-core PowerPC processor, released in 2001.
- POWER5 , a dual-core PowerPC processor, released in 2004.
- POWER6 , a dual-core PowerPC processor, released in 2007.
- POWER7 , has a 4.6.8-core PowerPC processor, released in 2010.
- POWER8 , has 12-core PowerPC processor, released in 2013.
- PowerPC 970 MP, a dual-core PowerPC processor, used in the Apple Power Mac G5 .
- Xenon , a triple-core, SMT- capable, PowerPC microprocessor used in the Microsoft Xbox 360 game console.
- z10 , quad-core z / Architecture processor, released in 2008
- z196 , quad-core z / Architecture processor, released in 2010
- zEC12 , a six-core z / architecture processor, released in 2012
- z13 , an eight-core z / architecture processor, released in 2015
- Danube, a dual-core, MIPS-based, home gateway processor.
- Atom , single, dual-core and quad-core processors for netbook, tablets and smartphones systems.
- Celeron Dual-Core , the first dual-core processor for the budget / entry-level market.
- Core Duo , a dual-core processor.
- Core 2 Duo , a dual-core processor.
- Core 2 Quad , 2 dual-core dies packaged in a multi-chip module.
- Core i3 , Core i5 , Core i7 and Core i9 family of dual-, quad-, 6-, 8-, 10-, 12-, 16-, and 18-core processors, the successor of the Core 2 Duo and the Core 2 Quad .
- Itanium 2 , a dual-core processor.
- Pentium D , 2 single-core dies packaged in a multi-chip module.
- Pentium Extreme Edition , 2 single-core dies packaged in a multi-chip module.
- Pentium Dual-Core , a dual-core processor.
- Teraflops Research Chip (Polaris), a 3.16 GHz, 80-core prototype processor, which the company originally reportedly would be released by 2011. 
- Xeon dual-, quad-, 6-, 8-, 10-, 12-, 14-, 15-, 16-, 18-, 22-, and 24-core processors.    
- Xeon Phi 57-core, 60-core and 61-core processors.
- SEAforth 40C18, a 40-core processor 
- SEAforth24, a 24-core processor designed by Charles H. Moore
- MPPA-256 , 256-core processor, released 2012 (256 usable VLIW cores, Network-on-chip (NoC), 32/64-bit IEEE 754 compliant FPU)
- NetLogic Microsystems
- XLP, has 32-core, quad-threaded MIPS64 processor
- XLR, an eight-core, quad-threaded MIPS64 processor
- XLS, an eight-core, quad-threaded MIPS64 processor
- GeForce 9 multi-core GPU (8 cores, 16 scalar stream processors per core)
- GeForce 200 multi-core GPU (10 cores, 24 scalar stream processors per core)
- Tesla multi-core GPGPU (10 cores, 24 scalar stream processors per core)
- Parallax Propeller P8X32 , an eight-core microcontroller.
- picoChip PC200 series 200-300 cores per device for DSP & wireless
- Plurality HAL series tightly coupled 16-256 cores, L1 shared memory, hardware synchronized processor.
- Kilocore KC256 report , has 257-core microcontroller with a core PowerPC and 256 8-bit “processing elements”.
- SiCortex “SiCortex node” has six MIPS64 cores on a single chip.
- Sony / IBM / Toshiba ‘s Cell processor, a nine-core processor with one general purpose PowerPC core and eight Specialized SPUs (Synergystic Processing Unit) optimized for vector operations used in the Sony PlayStation 3
- Sun Microsystems
- MAJC 5200, two-core VLIW processor
- UltraSPARC IV and UltraSPARC IV +, dual-core processors.
- UltraSPARC T1 , an eight-core, 32-thread processor.
- UltraSPARC T2 , an eight-core, 64-concurrent-thread processor.
- UltraSPARC T3 , has sixteen-core, 128-concurrent-thread processor.
- SPARC T4 , an eight-core, 64-concurrent-thread processor.
- SPARC T5 , has sixteen-core, 128-competitor-thread processor.
- Texas Instruments
- TMS320C80 MVP , a five-core multimedia video processor.
- TMS320TMS320C66, 2,4,8 core dsp.
- TILE64 , a 64-core 32-bit processor
- TILE-Gx , a 72-core 64-bit processor
- XMOS Software Defined Quad-core Silicon XS1-G4
- MIT , 16-core RAW processor
- University of California, Davis , Asynchronous Array of Simple Processors (AsAP)
- 36-core 610MHz AsAP
- 167-core 1.2GHz AsAP2
- University of Washington , Wavescalar processor
- University of Texas, Austin , TRIPS processor
- Linköping University , Sweden, ePUMA processor
- UC Davis , KiloCore, has 1000 core 1.78 GHz processor on 32 nm IBM process 
The research and development of multicore processors often compares many options, and benchmarks are developed to help such evaluations. Existing benchmarks include SPLASH-2, PARSEC, and COSMIC for heterogeneous systems. 
- ^ Digital signal processors(DSPs) have used multi-core architectures for much longer than high-end general-purpose processors. A typical example of a DSP-specific implementation would be a combination of aRISCCPU and a DSPMPU. This allows for the design of products that require a general-purpose processor for user interfaces and a DSP for real-time data processing; this type of design is common inmobile phones. In other applications, a growing number of companies have developed multi-core DSPs with very large numbers of processors.
- ^ Two kinds ofoperating systemsare reliable to use a dual-CPU multiprocessor: partitioned multiprocessing andsymmetric multiprocessing(SMP). In a partitioned architecture, each processor boots into separate segments of physical memory and operates independently; in an SMP OS, processors work in a shared space, executing threads within the OS independently.
- Race condition
- Multicore Association
- Parallel random access machine
- Partitioned global address space (PGAS)
- CPU shielding
- OpenCL (Open Computing Language) – a framework for heterogeneous execution
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