In computer engineering , a load / store architecture is an instruction set architecture that divides instructions into two categories: memory access ( load and store between memory and registers ), and ALU operations (which only occur between registers).  : 9-12
RISC instruction sets such architectures as PowerPC , SPARC , RISC-V , ARM , and MIPS are load / store architectures.  : 9-12
For instance, in a load / store approach both operands and destination for an ADD operation must be in registers. This differs from a register memory architecture (for example, a CISC instruction set architecture such as x86 ) in which one of the operands for the ADD operation may be in memory, while the other is in a register.  : 9-12
The earliest example of a load / store architecture was the CDC 6600 .  : 54-56 Almost all vector processors (including many GPUs  ) use the load / store approach. 
- Load-store unit (computing)
- Register memory architecture
- ^ Jump up to:a b c d Michael J. Flynn (1995). Computer architecture: pipelined and parallel processor design . ISBN 0867202041 .
- Jump up^ “AMD GCN reference” (PDF) .
- Jump up^ Harvey G. Cragon (1996). Memory systems and pipelined processors . p. 512-513. ISBN 0867204745 .