Load / store architecture

In computer engineering , a load / store architecture is an instruction set architecture that divides instructions into two categories: memory access ( load and store between memory and registers ), and ALU operations (which only occur between registers). [1] : 9-12

RISC instruction sets such architectures as PowerPC , SPARC , RISC-V , ARM , and MIPS are load / store architectures. [1] : 9-12

For instance, in a load / store approach both operands and destination for an ADD operation must be in registers. This differs from a register memory architecture (for example, a CISC instruction set architecture such as x86 ) in which one of the operands for the ADD operation may be in memory, while the other is in a register. [1] : 9-12

The earliest example of a load / store architecture was the CDC 6600 . [1] : 54-56 Almost all vector processors (including many GPUs [2] ) use the load / store approach. [3]

See also

  • Load-store unit (computing)
  • Register memory architecture

References

  1. ^ Jump up to:d Michael J. Flynn (1995). Computer architecture: pipelined and parallel processor design . ISBN  0867202041 .
  2. Jump up^ “AMD GCN reference” (PDF) .
  3. Jump up^ Harvey G. Cragon (1996). Memory systems and pipelined processors . p. 512-513. ISBN  0867204745 .

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