IBM System / 360 architecture

The IBM System / 360 architecture is the independent architectural model for the entire S / 360 line of computers . The elements of the architecture are documented in the IBM System / 360 Principles of Operation [1] [2] and the IBM System / 360 I / O Interface Channel to Control Unit Original Equipment Manufacturers Information manuals. [3]

Features

IBM S / 360 registers
3 . . . 7 . . . 1 . . . 5 . . . 00 (bit position) *
General-purpose registers
0 R0
1 R1
2 R2
3 R3
4 R4
5 R5
6 R6
7 R7
8 R8
9 R9
10 R10
11 R11
12 R12
13 R13
14 R14
15 R15
Floating-point registers
FP0 FP0
FP2 FP2
PF4 PF4
FP6 FP6
Program status word / Instruction address
PSW (40 bits) IA (24 bits) P rogram S tatus W ord
  • Note that IBM documentation numbers the bits in reverse order to that shown

above, ie, the most significant (leftmost) bit is designated as bit number 0.

The System / 360 architecture provides the following features:

  • 16 32-bit general-purpose registers
  • 4 64-bit floating-point registers
  • 64-bit processor status register (PSW), which includes a 24-bit Instruction Address
  • 24-bit (16 MB) byte-addressable memory space
  • Big-endian byte / word order
  • standard set instruction , including fixed-point binary arithmetic and logical instructions, present on all System / 360 models (except the model 20, see below).
– A commercial instruction set , adding decimal arithmetic instructions, is optional on some models, as is a scientific instruction set , which adds floating-point instructions. The universal instruction set includes all of the above plus the storage protection instructions and is standard for some models.
The Model 44 provides a few unique instructions for data acquisition and real-time processing.
– The Model 20 offers a stripped-down version of the standard instruction set with halfword (16-bit) instructions only plus the commercial instruction set and unique instructions for input / output.
– The Model 67 includes some instructions to handle 32-bit addresses and “dynamic address translation” with additional privileged instructions to provide virtual memory. [4]

Memory

Memory ( storage ) in System / 360 is addressed in terms of 8-bit bytes. Various instructions we operate larger units called Expired halfword (2 bytes), fullword (4 bytes), doubleword (8 bytes), quad word (16 bytes) and 2048 byte storage block, Specifying the leftmost (lowest address) of the unit. Within a halfword, fullword, doubleword or quadword, low numbered bytes are more significant than high numbered bytes; this is sometimes referred to as a big-endian . Many uses for these units require alignment on the corresponding boundaries. Within this article the term unqualified word Refers to a fullword .

The architecture of System / 360 provided for up to 24 = 16,777,216 bytes of memory; However, the Model 67 extended the architecture and allowed 2 32 = 4,294,967,296 [NB 1] bytes of virtual memory.

Addressing

System / 360 uses truncated addressing. That means that instructions do not contain complete addresses, but rather specify a base register and a positive offset from the addresses in the base registers. In the box of System / 360 the general address of the general registers [NB 2] . In some instructions, for example shifts, the same computations are performed for 32-bit quantities that are not addresses.

Data formats

The S / 360 architecture defines formats for characters, integers, decimal integers and hexadecimal floating point numbers. Decimal Arithmetic and Floating Point Arithmetic features are mandatory, but decimal and floating point instructions.

  • Characters are stored as 8-bit bytes.
  • Integers are stored as two full complement binary halfword or fullword values.
  • Packed decimal numbers are stored as 1-16 8-bit bytes containing an odd number of decimal digits followed by a 4-bit sign. Sign values ​​of hexadecimal A, C, E and F are positive and sign values ​​of hexadecimal B and D are negative. Digit values ​​of hexadecimal and values ​​of 0-9 are invalid, but the PACK and UNPK instructions are not valid.
  • Zoned decimal numbers are stored as 1-16 8-bit bytes, each containing a field in bits 0-3 and a digit in bits 4-7. The zone of the rightmost byte
  • Floating point numbers are only stored as fullword or doubleword values ​​on older models. On the 360/85 [5] and 360/195 [6] there are also extended precision floating point numbers stored as quadwords. For all three formats, 0 bit is a sign and bits 0-7 are a characteristic (exponent, biased by 64). Bits 8-31 (8-63) are a hexadecimal fraction. For extended precision, the low order has its own sign and characteristic, which are ignored on input and generated on output.

Instruction formats

Instructions in the S / 360 are two, four or six bytes in length, with the opcode in byte 0. Instructions have one of the following formats:

  • RR (two bytes). General byte 1 specified two 4-bit register numbers, but in some cases, eg, SVC, byte 1 is a single 8-bit immediate field.
  • RS (four bytes). Byte 1 specified two register numbers; bytes 2-3 specify a base and displacement.
  • RX (four bytes). Byte 1 bit 0-3 specified either a register number or a modifier; byte 1-bit 4-7 specified the number of the general register to be used as an index; bytes 2-3 specify a base and displacement.
  • IF (four bytes). Byte 1 specified an immediate field; bytes 2-3 specify a base and displacement.
  • SS (six bytes). Byte 1 specified two 4-bit length fields or one 8-bit length field; bytes 2-3 and 4-5 each specify a base and displacement. The encoding of the length is length-1.

Instructions must be on a two-byte boundary in memory; hence the low-order bit of the instruction address is always 0.

Program Status Word (PSW)

The Program Status Word ( PSW ) [2] ( pp71-72 ) contains a variety of controls for the currently operating program

PSW format
[ hide ]Bits Contents Explanation
0-7 System Mask bit 0-5: enable channels 0-5, bit 6: enable all remaining channels, [NB 3] bit 7: enable External interrupts (timer, interrupt key, and external signal) PoOps ( p71 )
8-11 Key protection CPU protection key to compare against storage
12 ASCII mode enable ASCII mode for packed decimal instructions, never used by IBM software [NB 4]
13 Machine checks enable Machine check interrupts
14 Wait State processor is halted, an interrupt, if enabled, will cause the processor to resume executing instructions
15 Problem state enable to prevent the use of instructions for supervisor state
16-31 Interruption Code code to indicate the type of interrupt, inserted when the PSW is stored, during IPLoad, this is the address of the device was loaded PoOps ( p77 )
32-33 Length Code Instruction length in halfwords or 0 if unavailable
34-35 Condition Code see individual instructions for encoding
36-39 Program Mask bit 36: enable fixed-point overflow, bit 37: decimal overflow, bit 38: exponent underflow, bit 39: significance PoOps ( p71 )
40-63 Address Instruction address of next instruction, except for a program interrupts with ILC 0

The Program Status Word ( LPSW ) is a privileged statement that loads the Status Program Word (PSW), including the program mode, key protection, and the address of the next instruction to be executed. LPSW is most often used to “return” from an interrupt by “PSW” which is associated with the interrupt class. Other privileged instructions (eg, SSM, STNSM, STOSM, SPKA, etc.) are available for manipulating subsets of the PSW without causing an interruption or loading to PSW; and one non-privileged instruction (SPM) is available for manipulating the program mask.

Interruption system

An interruption is a mechanism for automatically changing the program state; it is used for both synchronous [NB 5] and asynchronous events. The architecture [2] ( pp77-83 ) defines 5 classes of interruption. There are two storage fields assigned to each class of interruption on the S / 360; an old PSW double-word and a new PSW double-word. The processor stores the PSW, with an interruption code inserted, into the old PSW rental and then loads PSW from the new PSW rental. This is an instruction address, thus effecting a branch, and (possibly) sets and / or resets other fields within the PSW, thus effecting a mode change.

The S / 360 architecture defines a priority to each interrupt class, but it is only relevant when two interrupts occur simultaneously; An interrupt routine may be interrupted by any other enabled interrupt, including another occurrence of the initial interrupt. For this reason, it is normal practice to specify all of the mask bits, with the exception of machine-check mask bit, as 0 for the “first-level” interrupt handlers. “Second-level” interrupts (multiple occurrences of interrupts of the same interrupt class).

[ hide ]Class break Old PSW
hex dec
New PSW
hex dec
Priority
Input / Output PoOps ( pp78-79 ) 38 56 78,120 4
Program PoOps ( pp79-80.1 ) 28 40 68,104 2
Supervisor Call PoOps ( pp80.1-81 ) 20 32 60 96 2
External PoOps ( pp81-82 ) 18 24 58 88 3
Machine Check PoOps ( pp82-83 ) 30 48 70,112 1

Input / Output interruption

An I / O interrupt PoOps ( pp78-79 ) occurs at the completion of a channel program, after fetching a CCW with the PCI bit set and also for asynchronous events detected by the device, control unit or channel, eg, completion of a mechanical movement. The system stores the device in the break code and stores channel status at the CSW at location 64 (’40’X).

Program interruption

A program interrupt [2] ( pp16,79-80.1 ) occurs when an encounter encounters one [NB 6] of 15 [NB 7] exceptions; However, if the program Mask is corresponding to an exception is 0 then there is no interrupt for that exception. On 360/65, [9] ( p12 ) 360/67 [7] ( p46 ) and 360/85 [5] ( p12 ) the Protection Exception and Addressing Exception interrupts can be imprecise, in which case they store an Instruction Length Code of 0. The Interruption code may be any of

Interruption codes for Program interrupts
old PSW bits 26-31
[ hide ]hex
bits 26-31
Dec Exception
0 0 Imprecise interrupt [NB 6] on 360/91, [8] ( p15 ) 360/95 or 360/195 [6] ( p14 )

Old PSW bits for multiple imprecise interrupt codes
[ show ]bit Exception
1 1 Operation PoOps ( p79 )
2 2 Privileged operation PoOps ( p79 )
3 3 Execute PoOps ( p79 )
4 4 PoOps Protection ( p79 )
5 5 Addressing PoOps ( pp79-80 )
6 6 PoOps specification ( p80 )
7 7 Data PoOps ( p80 )
8 8 Fixed-point overflow PoOps ( p80 )
9 9 Fixed-point divide PoOps ( p80 )
AT 10 Decimal overflow PoOps ( p80 )
B 11 Decimal divide PoOps ( p80 )
C 12 Exponent overflow PoOps ( p80 )
D 13 Exponent underflow PoOps ( p80 )
E 14 Significance PoOps ( p80 )
F 15 Floating-point divide PoOps ( p80.1 )
10 16 Segment Translation [7] ( p17 ) [NB 7]
11 17 Page Translation [7] ( p17 ) [NB 7]
12 18 SSM Exception [9] [NB 7]
  • An operation exception PoOps ( p79 ) is recognized when a program attempts to execute an instruction with an opcode that the computer does not implement. In particular, an operation exception is recognized when a program is written for an optional feature, eg, floating point, that is not installed.
  • privileged operation exception PoOps ( p79 ) is recognized when a program attempts to execute a privileged instruction when the problem state in the PSW is 1.
  • An Exception Exception PoOps ( p79 ) is recognized when the operand of an EXECUTE statement is another EXECUTE statement.
  • In exceptional protection Poops ( p79 ) is reconnu When A program Attempts to store into a location Whose storage protect key does not match [Note 10] the PSW key, or to fetch from a fetch protected location Whose storage protect key does not match the PSW key.
  • An exception Exception PoOps ( pp79-80 ) is recognized when a program attempts to access a storage location is not currently available. This normally occurs with an address beyond the capacity of the machine, but it is also possible that machines are allowed to be taken offline.
  • exception exception PoOps ( p80 ) is recognized when an instruction has a length or register field with values ​​not permitted by the operation, or when it has an operand address that does not satisfy the alignment requirements of the opcode, eg, a LH instruction with an odd operand address on a machine without the byte alignment feature.
  • data exception Poops ( p80 ) is recognized when a decimal statement specifies invalid operands, eg, invalid data, invalid overlap.
  • fixed-point overflow exception PoOps ( p80 ) is recognized when significant bits are lost in a fixed point arithmetic or shift instruction, other than divide.
  • fixed-point exception divide PoOps ( p80 ) is recognized when significant bits are lost in a fixed-point divide or Convert to Binary instruction.
  • decimal overflow exception PoOps ( p80 ) is recognized when significant digits are lost in a decimal arithmetic instruction, other than divide.
  • decimal exception exception PoOps ( p80 ) is recognized when significant bits are lost in a decimal divide statement. The destination is not altered.
  • An exponent overflow exception PoOps ( p80 ) is recognized when the characteristic in a floating-point arithmetic operation exceeds 127 and the fraction is not zero.
  • An exponent underflow exception PoOps ( p80 ) is recognized when the characteristic in a floating-point arithmetic operation is negative and the fraction is not zero.
  • exception exception PoOps ( p80 ) is recognized when the fraction in a floating-point add or subtract operation is zero.
  • floating-point divide exception PoOps ( p80.1 ) is recognized when the fraction in the divisor of a floating-point divide operation is zero.

Supervisor Call interruption

A Supervisor Call Interrupt PoOps ( pp80.1-81 ) occurs as a result of a Supervisor Call instruction; the system stores bits 8-15 of the SVC instruction as the Interruption Code.

External interrupt

An External PoOps ( p81 ) [NB 11] interruption occurs as the result of certain asynchronous events. Bits 16-24 of the External Old PSW are set to 0 and one more 24-31 is set to 1

Interruption codes for External interrupts
[ hide ]PSW bit Type of external interruption
24 Timer
25 Interrupt key
26 External signal 2
Malfunction alert on 360/65 [9] in multisystem mode
27 External signal 3
System Call on 360/65 [9] in Multisystem mode
28 External signal 4
29 External signal 5
30 External signal 6
31 External signal 7

Machine Check interruption

A Machine Check Interrupt PoOps ( pp82-83 ) appears to report unusual conditions associated with the channel or CPU that can not be reported by another class of interrupt. The most important class of conditions of machine inspection is a machine error, such as this one, but it does not allow for less serious conditions. Both the interrupt code and the data stored in the 80’x (128 decimal) are model dependent.

Input / Output

This article describes I / O from the CPU perspective. It does not discuss the channel cable or connectors, but there is a summary elsewhere and can be found in the IBM literature. [3]

I / O is carried out by a conceptually separate processor called a channel. Channels have their own instruction set, and access memory independently of the program running on the CPU. On the smaller models (through 360/50 ) a single microcode engine runs both the CPU program and the channel program. On the larger models the channels are in separate cabinets and have their own interfaces to memory. A channel may contain multiple subchannels , each containing the status of an individual channel program. A subchannel associated with multiple devices CONCURRENTLY That can not-have channel programs is Referred to as shared ; a subchannel representing a single device is referred to as unshared .

There are three types of channels on the S / 360:

  • byte multiplexer channel is capable of multiple executing CCW s concurrently; it is normally used to connect the device and the card reader. A byte multiplexer channel can have a number of subchannel selects, each with a single subchannel, which behave like low-speed selector channels.
  • selector channel has only one single subchannel, and hence is only capable of executing one channel command at a time. It is normally used in the process of blocking the connection, such as magnetic tape drives.
  • block multiplexer channel is capable of concurrently running multiple channel programs, but only one at a time can be active. The control unit can request suspension at the end of a channel command and can later request resumption. This is intended for devices in which it is a mechanical delay after completion of data transfer, eg, for search on moving-head DASD. The block multiplexer channel was a late addition to the System / 360 architecture; early machines had only byte multiplexing channels and selector channels. The block multiplexer channel was an optional feature only on the models 85 and 195. The block multiplexor channel was also available on the later System / 370 computers.

Conceptually peripheral equipment is attached to a S / 360 through control unit , which is connected to channels. However, the architecture does not require that control mechanisms be separate, and they are in practice. Similarly, the architecture does not require the separate channels of the processor, and the smaller S / 360 models (through 360/50) have integrated channels that steal cycles from the processor.

Peripheral devices are addressed with 16-bit [NB 12] addresses., [2] ( p89 ) referred to as cua or cuu ; this article will use the term cuu . The high 8 bits identify a channel, numbered from 0 to 6, [NB 3] while the low 8 bits identify a device on that channel. A device may have multiple cuu addresses.

Control units are assigned an address “capture” range. For example, a CU might be assigned range 20-2F or 40-7F. The purpose of this is to assist with the connection and prioritization of multiple control units to a channel. For example, 20-2F, 50-5F, and 80-8F. Not all of the data are required for an assigned physical device. Each control unit is also marked as High or Low priority on the channel.

Device selection progresses from the channel to each control unit in the order they are physically attached to their channel. At the end of the chain, the process continues in reverse back to the channel. If the selection returns to the channel then, it is necessary to control the value of the output. If so, then the I / O was processed. If not, then the selection is passed to the next outbound CU. Control units marked as Low priority for inbound (returning) CUU to be within their range. If so, then the I / O is processed. If not, then the selection is passed to the next inbound CU (or the channel). The connection of three controls unit to a channel might be physically -ABC and, If all are marked as High then the priority would be ABC. If all are marked low then the priority would be CBA. If B was marked High and AC low then the order would be BCA. Extending this line of reasoning to the first of N controllers would be priority 1 (High) or 2N-1 (Low), the second priority 2 or 2N-2, the third priority 3 or 2N-3, etc. The last physically attached would always be priority N.

There are three storage fields reserved for I / O; a double word I / O old PSW, a doubleword I / O new PSW and a fullword Channel Address Word ( CAW ). Performing an I / O normally requires the following:

  • initializing the CAW with the storage key and the address of the first CCW
  • issuing a Start I / O ( SIO ) statement that specifies the cuu for the operation
  • waiting [NB 13] for an I / O interrupt
  • handling any unusual conditions indicated in the Channel Status Word ( CSW )

A channel program Consists of a sequence of Channel Control Words ( CCW s) chained together (see below.) Normally the channel fetches CCW s from consecutive doublewords, goal control unit directly can the channel to skip a CCW and a Transfer In Channel ( ICT ) CCW can direct the channel to start fetching CCW s from a new location.

There are several defined ways for a channel to complete. Some of these allow the channel to continue fetching CCWs, while others terminate the channel program. In general, if the CCW does not have the chain-command set and is not a TIC, then the channel will terminate the I / O operation and cause an I / O interrupt when the command completes. Some status bits of the suppress chaining unit.

The most common ways in the world for the purpose of being more efficient and more effective. If Suppress-Length-Indication (SLI) is not set, and chaining is not allowed. The most common situations that suppress chaining are unit-exception and unit-check. However, the combination of unit-check and status-modify does not suppress chaining; rather, it causes the channel to be retrying, reprocessing the same CCW.

In addition to the signal interruption to the CPU when an I / O operation is complete, a channel can also send a Program-Controlled Interrupt (PCI) to the CPU while the channel program is running, without terminating the operation, and a delayed device-end interrupt after the I / O completion interrupt.

Channel status

These conditions are detected by the channel and indicated in the CSW . PoOps ( pp116-118 )

  • Program-controlled PoOps Interrupt ( pp116-117 )indicates that the channel has fetched a CCW with the PCI bit set. The channel continues processing; this interrupt simply informs the CPU of the channel’s progress. An example of the use of program-controlled interrupt is in the “Program Fetch” function. To ensure that this record has been completely read, a “disabled bit spin”, one of the few remaining ones in the control program, is initiated. Satisfaction of the spin indicates that the Control / Relocation Record is completely in hand storage and the first preceding Text Record may be relocated. After relocation, NOP CCW is changed to a continuous ICT and channel program. In this way,EXCP , and possibly only one revolution of the disk drive. PCI also has applications in teleprocessing access method buffer management.
  • Incorrect length PoOps ( p117 ) indicates that the data transfer has been completed before the Count was exhausted. This indication is suppressed if the Suppress-Length-Indication bit in the CCW is set.
  • Program check PoOps ( p117 ) indicates one of the following errors
    • Nonzero bits where zeros are required
    • An invalid data or CCW address
    • The CAW or a TIC refers to a TIC
  • Protection check PoOps ( pp117-118 ) indicates that the protection key in the CAW is non-zero and does not match the storage protection key.
  • Channel data check PoOps ( p118 ) indicates a parity error during a data transfer.
  • Channel control check PoOps ( p118 ) indicates a channel malfunction other than Channel data check or Interface control check .
  • Interface control check PoOps ( p118 ) indicates an invalid signal in the channel to control unit interface.
  • Chaining check PoOps ( p118 ) indicates lost data during data chaining.

Unit status

These conditions are presented to the channel by the control unit or device. PoOps ( pp113-116 ) In some cases they are handled by the channel and in other cases they are indicated in the CSW . There is no distinction between conditions detected by the device and conditions detected by the device.

  • Warning PoOps ( p113 ) indicates an unusual condition not associated with an ongoing channel program. It often states that the CPU would respond by issuing a read-type command, most often a sense command (04h) from which additional information could be deduced. Attention is a special condition, and requires specific operating support, and for which the operating system has a special “attention index” table.
  • Status edit PoOps ( pp113-114 ) (SM) indicates one of three unusual conditions
    • A Test I / O instruction was issued to a device that does not support it.
    • A Busy status refers to the control unit rather than to the device.
    • A device has a condition that requires skipping a CCW. A CCW with a command for which Status is not possible or an interruption.
A typical channel program where SM is
 ...
 Search Id Equal
 TIC * -8
 Read Data
where the ICT causes the channel to refess the search until the device indicates a successful search by raising SM.
  • Control unit end PoOps(p114) indicates that a previous control unit busy status has been cleared.
  • Busy PoOps ( pp114-115 ) indicates that a device ( SM = 0) or a control unit ( SM = 1) is busy.
  • Channel end PoOps ( p115 ) indicates that the device has completed the data transfer for a channel command. There may also be an incorrect length indication where the field of the CCW is exhausted, depending on the value of the Suppress-Length-Indication bit.
  • Device end PoOps ( p115 ) indicates that the device has completed operation and is ready to accept another. May be signalled OF CONCURRENTLY with EC or May be delayed.
  • Unit check PoOps ( pp115-116 ) indicates that the device or control unit has detected an unusual conditions and that details can be obtained by issuing a Sense command.
  • Unit exception PoOps ( p116 ) indicates that the device has detected an unusual condition, eg, end of file.

Channel Address Word

The fullword Channel Address Word [2] ( p99 ) (CAW) contains a 4-bit storage protection key and a 24-bit address of the channel program to be started.

Channel Command Word

Channel Command Word is a doubleword containing the following:

  • an 8-bit channel Command Code PoOps ( p100 )
  • has 24-bit address PoOps ( pp100-101 )
  • a 5-bit flag field PoOps ( pp99-100,101-105 )
  • an unsigned halfword Count field PoOps ( pp100-101 )

CCW Command codes

The low order 2 or 4 bits determines the six types of operations that the channel performs. [2] ( pp100,105 ) The encoding is

CCW Command codes
[ hide ]bits Command
**** 0000 Invalid in a CCW, simulated by the processor’s Test I / O (TIO) instruction
MMMM 0100 Sense PoOps ( pp106-107 )
**** 1000 Transfer in Channel (ICT) PoOps ( pp107-108 )
MMMM 1100 Read Backward PoOps ( pp105-106 )
MMMM MM01 Write PoOps ( p105 )
MMMM MM10 Read PoOps ( p105 )
MMMM MM11 Control PoOps ( pp106-107 )

The meaning of the high order six or four bits, the modifier bits, M in the table above, depends on the type of I / O device attached, see eg, DASD CKD CCWs . All eight bits are sent to the device (or its functional equivalent).

Control is used to cause a change in a device or control unit, often associated with mechanical motion, eg, rewind, seek.

Sense is used to read data describing the status of the device. The most important case is that when it is terminated with a specific test, the specific cause can be determined by a test. A Sense command with the edit bit all zero is always valid.

A noteworthy deviation from the architecture is that DASD uses Sense Command codes for Reserve and Release, instead of using Control.

CCW flags

The flags in CCW affect how it executes and terminates.

CCW flags
[ hide ]bit flag effect
32 CD Chain-Data Continue operation using the storage area defined by the next CCW. PoOps ( pp101-103 )
33 DC Chain-Command Continue with the Command in the next CCW. PoOps ( pp101,103 )
34 SLI[NB 14] Suppress-Length-Indication Continue channel program after count mis-match. PoOps ( pp99-100 )
35 SKIP Skip Do not read from or write into storage. PoOps ( pp103-104 )
36 PCI Program-Controlled-Interruption Request interruption when fetching CCW. PoOps ( pp104-105 )

Channel Status Word

The Channel Status Word (CSW) [2] ( pp113-121 ) provides data associated with an I / O interrupt.

CSW format
[ hide ]bits field
0-3 Key PoOps ( p119 )
4-7 0000
8-31 Command Address PoOps ( p119 )
32-47 Status PoOps ( pp113-118 )
32-39
Unit Status Conditions PoOps ( pp113-116 )
Detected by the device or control unit
32
Attention PoOps ( p113 )
33
Status edit PoOps ( pp113-114 )
34
Control unit end PoOps ( p114 )
35
Busy PoOps ( pp114-115 )
36
Channel end PoOps ( p115 )
37
Device end PoOps ( p115 )
38
Unit check PoOps ( pp115-116 )
39
Exception Unit PoOps ( p116 )
40-47
Channel Status Conditions PoOps ( pp116-118 )
Detected by the channel.
40
Program-controlled PoOps Interrupt ( pp116-117 )
41
Incorrect length PoOps ( p117 )
42
Program check PoOps ( p117 )
43
Protection check PoOps ( pp117-118 )
44
Channel data check PoOps ( p118 )
45
Channel control check PoOps ( p118 )
46
Interface control check PoOps ( p118 )
47
Chaining check PoOps ( p118 )
48-63 Count PoOps ( p120 )
  • The Protection Key field contains the protection of the CAW at the time that the I / O operation was initiated for I / O complete or PCI interrupts. PoOps ( p119 )
  • The Command Address field contains the address + 8 of the last CCW fetched for an I / O complete or PCI interrupt. However, there are 9 PoOps exceptions . ( p119 )
  • The Status field contains one byte of Channel status bits, indicating conditions detected by the PoOps channel , ( pp116-118 ) and one byte of Unit status bits, indicating conditions detected by the I / O unit PoOps . ( pp113-116 ) There is no distinction between conditions detected by the device and conditions detected by the device.
  • The Residual Count is a half word that gives the number of bytes in the area described by the PoOps . ( p120 ) The difference between the count in the CCW and the residual count gives the number of bytes transferred.

Operator controls

The architecture of System / 360 specifies the existence of several common functions, but did not specify their means of implementation. This is an alternative to using different physical means, eg, dial, keyboard, pushbutton, roller, image or text on a CRT, for selecting the functions and values ​​on different processes. Any reference to key or switch should be applied to, eg, a light-pen selection, an equivalent keyboard sequence.

  • System Reset sends a reset signal on every channel and clears the processor state; all pending interruptions are canceled. System Reset is not guaranteed to be correct in general registers, floating point registers or storage. System Reset does not reset the state of shared I / O devices.
  • Initial Program Load (IPL) PoOps ( p123 ) is a process for loading a program where there is a loader available in storage, usually because the machine was just powered on or to load an alternative operating system. [2] ( p123 ) This process is sometimes known as Booting .
As part of the IPL facility the operator has a means of specifying a 12-bit [NB 3] device, typically with three dials as shown in the operator controls drawing. When the operator [NB 15] selects the Load function, the system performs a System Reset , sends a Read IPL [NB 16] channel to the selected device to read 24 bytes into locations 0-23 and causes the channel to begin CCW fetchings at location 8; Command Chaining + Suppress Length Indication. CCW with a length of 24, and address of 0 and the flags containing Command Chaining + Suppress Length Indication. At the completion of the operation, the system stores the PSW from location 0.
Initial program loading is typically done from a tape, a card reader, or a disk drive. Generally, the operating system was loaded from a disk drive; IPL from tape or cards was used only for diagnostics or for an operating system on a new computer.
  • Emergency pullover PoOps ( p124 ) sends an EPO signal to every I / O channel, then turns off power to the complex processor. Because EPO bypasses the normal sequencing of power down, damage can result, and the EPO control has a mechanical latch to ensure that a customer engineer inspects the equipment before attempting to power it back on.
  • Power on PoOps ( p124 ) powers up all components of the complex processor and performs a system reset.
  • Power off PoOps ( p124 ) initiates an orderly power-off sequence. Although the contents of storage are preserved, the associated storage may be lost.
  • The Interrupt key PoOps ( p124 ) causes an external interruption with bit 25 set in the External Old PSW.
  • The Wait light PoOps ( p124 ) indicates that the PSW has bit 14 (wait) set; the processor is a halide but resumes operation when an interrupt condition occurs.
  • The Manual light PoOps ( p124 ) indicates that the CPU is in a stopped state.
  • The Light System PoOps ( p124 ) indicates that a meter is running, either due to CPU activity or due to I / O channel activity.
  • The Test Light PoOps ( p124 ) indicates that certain operator controls are active, when certain facilities, eg, instruction, have been used by a diagnosis or when abnormal thermal conditions exist. The details are model dependent.
  • The Load light PoOps ( p124 ) is powered by IPL and external start. It is powered by PSW from location 0 at the completion of the load process.
  • The Load Unit PoOps ( pp124-125 ) provides the rightmost 11 [NB 17] bits of the device from which to perform an IPL.
  • The PoOps Load Key p125 ) starts the IPL sequence.
  • The Prefix Select Key Switch PoOps ( p125 ) selects whether the IPL would use the primary prefix or the alternative prefix.
  • The System-Reset Key PoOps ( p125 ) initiates a System Reset .
  • The Stop Key PoOps ( p125 ) puts the CPU in a stopped state; channel programs continue running and interruption conditions remain pending.
  • The PoOps Switch Rate p125 ) determines the mode in which the processor fetches instructions. Two modes are defined by the architecture:
    • PROCESS
    • INSTRUCTION STEP
  • The Start Key PoOps ( p125 ) initiates instruction fetching in accordance with the setting of the Rate Switch .
  • The Storage-Select PoOps Switch ( p126 ) determines the type of resource accessed by the Store Key and Display Key . Three selections are defined by the architecture:
    • Main storage
    • General registers
    • Floating-point registers
  • The Address Switches PoOps ( p126 ) specify the address or register number for the Key Store , Display Key and, on some models, the IC Key Set ..
  • The Data Switches PoOps ( p126 ) specify the data for the Key Store , and some models, the IC Key Set .
  • The Store Key PoOps ( p126 ) stores the value in the Data Switches as specified by the Storage-Select Switch and the Address Switches .
  • The Display Key PoOps ( p126 ) displays the value specified by the Storage-Select Switch and the Address Switches .
  • The Set IC = PoOps ( p126 ) sets the instruction address portion of the PSW from the Data Switches or the Address Switches , depending on the model.
  • The Address-Compare PoOps Switches ( p126 ) select the mode of comparison and what is compared. Stop on instruction address compare is present on all models.
  • The Alternate-Prefix Light PoOps ( p126 ) is in the alternate state.

Optional features

Byte-aligned operands

On some models the alignment requirements for some problem-state instructions were relaxed. There is no mechanism to turn off this feature, and programs must be modified.

Decimal arithmetic

The decimal arithmetic feature provides instructions on how to work with decimal data. A packed decimal number has 1-31 decimal digits followed by a 4-bit sign. All of the decimal arithmetic instructions except PACK and UNPACK generate a data exception if a digit is not in the range 0-9 or is not in the range AF.

Direct Control

The Direct Control PoOps ( p17.1 ) provides six external signal lines and an 8-bit data path to / from storage. [10]

Floating-point arithmetic

The floating-point arithmetic feature provides 4 64-bit floating point registers and instructions to operate on 32 and 64 bit hexadecimal floating point numbers. The 360/85 and 360/195 also support 128 bit extended precision floating point numbers.

Interval timer

If the interval timer feature [2] ( p17.1 ) is installed, the processor decrements the word at location 80 (’50’X) at regular intervals; 23 times per second 23 times per second. The smaller models have the same frequency (50 Hz or 60 Hz) as the AC power supply, but larger models have a high resolution timer feature. The processor causes an external interruption when the timer goes to zero.

Multi-system operation

Multi-system operation PoOps ( pp17.1-18 ) is a set of features to support multi-processor systems, eg, direct control , direct address relocation (prefixing).

Storage protection

If the storage protection feature [2] ( pp17-17.1 ) is installed, then there is a 4-bit storage key associated with every 2.048-byte block of storage and that key is checked when storing CPU or an I / O channel. A CPU or channel key of 0 disables the check; a nonzero CPU or channel key allows data to be stored in a block with the matching key.

Storage Protection was used to prevent the application of the application or the application of the operating system. This permitted testing is done along with production. Because the key was only four bits in length, the maximum number of applications was 15.

An additional option available on some models was fetch protection. It allowed the operating system to specify which blocks were protected from fetching as well as from storing.

Deviations and extensions

The System / 360 Model 20 is radically different and should not be considered as S / 360.

The System / 360 Model 44 is missing certain instructions, but a feature permits the use of standard S / 360 operating systems and applications.

Some models have features that extended the architecture, eg, emulation instructions, paging, and some models make minor deviations from the architecture. Examples include:

  • The multisystem feature on the S / 360-65 which modifies the behavior of the direct control feature of the Set System Mask (SSM) statement. [9]
  • The System / 360 Model 67 -2 had similar, but incompatible, changes. [7]

Some deviations served as prototypes for features of the S / 370 architecture.

See also

  • Memory protection key

Notes

  1. Jump up^ Twice the size of the later System / 370
  2. Jump up^ A specification of general register 0 yield a base address of zero Rather than the register happy.
  3. ^ Jump up to:c It is a processor that complies with the S / 360 architecture, the highest channel number is 6, 11 bits are sufficient to identify the 7 bits and are sufficient to provide masking of I / O interrupts. However, there are 360 ​​/ 67-2 with two 2846 Channel Controllers, channels are numbered 0-6 and 8-14; [7] ( p15 ) similarly, the 360/195 had an extended channel feature [6] ( p21 )but numbered the channels 0 through 13. [6] ( p25 )I / O interrupts for Channel Controller 1 on the 360 ​​/ 67-2 were used by the control system, and the 360/195 used bit 7 (Channel 6) of the System Mask. Interruptions from More than Seven Channels PoOps ( p121.4 ) describes the summary masking for additional channels, but other text in English. Standard software supported channels 0-F.
  4. Jump up^ Because the design of the S / 360 has occurred with the development of ASCII, IBM’s ASCII support did not match the standard that was eventually adopted.
  5. Jump up^ The S / 360 literature does not use the terms fault ortrap
  6. ^ Jump up to:b On the 360/91, [8] ( p15 ) 360/95 and 360/195 [6] ( p14 ) a Program interruption May Occur for multiple imprecise exceptions. The ILC in the Old PSW Program is 0, bits 26-31 are 0 and bits 16-27 There is no provision for multiple reporting occurrences of the same exception. Reporting of multiple imprecise exceptions is not part of the S / 360 architecture.
  7. ^ Jump up to:d There are 17 possible exceptions on the 360/67, [7] ( p17 ) but exception page is not part of the S / 360 architecture; similarly, interrupt code 18 (‘0012’X) we have 360/65 multiprocessor is not part of the S / 360 architecture.
  8. Jump up^ The Specification is not used for imprecise interruptions on the 360/195
  9. ^ Jump up to:b Not Used is 360/91
  10. Jump up^ A PSW key of 0 matches Any storage key.
  11. Jump up^ Even though a timer expiration is an internal event, it causes an External interruption and for this reason, this interruption is usually Referred to as a timer / external interrupt.
  12. Jump up^ S / 360 and early S / 370 software only used 12 bits to store device addresses.
  13. Jump up^ But continuing with unrelated work.
  14. Jump up^ Also known as Suppress Incorrect Length Indication (SILI)
  15. Jump up^ Or an equivalent automated facility.
  16. Jump up^ Read with all edit bits zero
  17. Jump up^ There is an inconsistency, en ce queInterrupts from More than Seven Channels Poops ( p121.4 )Allows for more channels.

References

  1. Jump up^ IBM (1964), IBM System / 360 Principles of Operation (PDF) , First Edition, A22-6821-0.
  2. ^ Jump up to:k IBM (September 1968), IBM System / 360 Principles of Operation (PDF) , Eighth Edition, A22-6821-7. Revised by IBM (May 12, 1970), ibid. , GN22-0354. and IBM (June 8, 1970), ibid. , GN22-0361.
  3. ^ Jump up to:b IBM, the IBM System / 360 I / O Interface Channel to Control Unit Original Equipment Manufacturers’ Information (PDF) , Fifth Edition, A22-6843-3.
  4. Jump up^ IBM Corporation (1974). IBM System / 360 System Summary (PDF) . p. 3-3 . Retrieved July 16, 2017 .
  5. ^ Jump up to:b IBM (June 1968), IBM System / 360 Model 85 Functional Characteristics (PDF) , SECOND EDITION, A22-6916-1.
  6. ^ Jump up to:e IBM (August 1970), IBM System / 360 Model 195 Functional Characteristics (PDF) , Second Edition, GA22-6943-1.
  7. ^ Jump up to:f IBM (February 1972), IBM System / 360 Model 67 Functional Characteristics (PDF) , Third Edition, GA27-2719-2.
  8. ^ Jump up to:b IBM (1968-03-18) IBM System / 360 Model 91 Functional Characteristics (PDF) , Third Edition, A22-6907-2.
  9. ^ Jump up to:e IBM (September 1968), “Appendix A. Multiprocessing System” IBM System / 360 Model 65 Functional Characteristics (PDF) , Fourth Edition, pp. 30-34, A22-6884-3.
  10. Jump up^ IBM, the IBM System / 360 Direct Control and External Interrupt Features Original Equipment Manufacturers’ Information , Third Edition, A22-6845-2.

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