Harvard architecture

The Harvard architecture is a computer architecture with PHYSICALLY separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on 24-bit wide punch and 24-bit data in electro-mechanical counters. These methods are provided in the central processing unit and provided to the storage as data instruction. Programs needed to be loaded by an operator; the processor could not initialize itself.

Today, the process of implementing the same signal, but actually implementing a modified Harvard architecture , so they can support tasks like loading a program from the storage of data and then executing it.

Memory details

In a Harvard architecture, there is no need to make the two features. In particular, the word width, timing, implementation technology, and memory address structure can differ. In some systems, instructions for pre-program tasks can be stored in memory while generally requires read-write memory . In some systems, there is much more instruction than memory data so statement addresses are wider than data addresses.

Contrast with von Neumann architectures

Main article: Von Neumann architecture

Under pure von Neumann architecture the CPU can be reading or writing / writing data from / to the memory. Both can not occur at the same time and use the same bus system. In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time, [1] even without a cache. A Harvard architecture computer can thus be faster for a given circuit because of information fetches and data access do not contend for a single memory pathway.

Also, a Harvard architecture machine has separate code and data address spaces: address zero is not the same as data address zero. Instruction address zero might identify a twenty-four bit value, while data address zero might indicate an eight-bit byte that is not part of that twenty-four bit value.

Contrast with modified Harvard architecture

Main article: Modified Harvard architecture

A modified Harvard architecture machine is very much like a Harvard architecture machine, but it relaxes the strict separation between instruction and data while still letting the CPU competitively access two (or more) memory nozzles. The most common modification includes separate instructions and data caches backed by a common address space. While the CPU executes from cache, it acts as a pure Harvard machine. When accessing backing memory, it acts like a Neumann machine (where code can be moved around like data, which is a powerful technique). This modification is widespread in modern processors, such as ARM architecture , Power Architecture and x86processors. It is sometimes loosely called a Harvard architecture, considering the fact that it is actually “modified”.

Another modification provides a pathway between the memory instruction (such as ROM or flash memory ) and the CPU to allow words from the instruction memory to be processed as read-only data. This technique is used in some microcontrollers, including the Atmel AVR . This allows constant data, such as text strings or function tables , to be accessed without first having to be copied into data memory, to preserve the memory (and power-hungry) data memory for read / write variables. Special Machine language instructions are Provided to read data from the memory instruction, or the instruction memory can be accessed using a peripheral interface ^. (English) The term is used for the purposes of the two mechanisms can substitute for each other.


In recent years, the speed of the CPU has grown in comparison to the speed of the main memory. Care needs to be taken into account in order to maintain performance. If, for instance, every instruction in the CPU requires an access to memory, the computer gains nothing for increased CPU speed-a problem referred to as memory being bound .

It is possible to make extremely fast memory, but it is only practical for small amounts of memory for cost, power and signal routing reasons. The solution is a CPU cache which holds recently accessed data. As long as the CPU is in the cache, the performance is much higher than it is when the cache is to get the data from the main memory.

Internal vs. external design

Modern high performance CPU chips incorporates Harvard and von Neumann architecture. In particular, the “split cache” version of the Harvard architecture is very common. Cache cache memory is a cache cache and a data cache. Harvard architecture is used as the CPU accesses the cache. In the case of a cache miss, however, the data is retrieved from the main memory, which is not formally divided into separate instructions and data sections, although it may be ) flash memory.

Thus, while a Neumann architecture is visible in some contexts, such as when data and code come through the same memory controller, the hardware implementation gains the efficiencies of the Harvard architecture for cache accesses and at least some main memory accesses.

In addition, CPUs often have write buffers which let CPUs proceed after writes to non-cached regions. The nature of the memory is then that the CPU and software must ensure that the data and instruction caches are written and written correctly.

Modern uses of the Harvard architecture

The main advantage of the pure Harvard architecture using modern CPU cache systems. Relatively pure Harvard architecture machines are used mostly in applications where trade-offs, like the cost and power savings from omitting caches, outweigh the programming penalties from separate code and data address spaces.

  • Digital signal processors (DSPs) generally execute small, highly optimized audio or video processing algorithms. They avoid caches because their behavior must be extremely reproducible. The difficulties of coping with multiple addresses are of secondary concern to speed of execution. Consequences, some SIMS and VLIW processing. Texas Instruments TMS320 C55x processors, for one example, multiple parallel data bus (two write, three read) and one bus instruction.
  • Microcontrollers are characterized by having small amounts of memory and data ( SRAM ), and take advantage of the Harvard architecture to speed processing by concurrent instruction and data access. The device can be used for different types of 16-bit wide instructions and 8-bit wide data. They also mean that instruction prefetch can be performed in parallel with other activities. Examples include the PIC by Microchip Technology, Inc. and the AVR by Atmel Corp. (now part of Microchip Technology).

Even in these cases, it is common to employ special instructions in the form of a program for reprogramming; These processors are modified Harvard architecture processors.


  1. Jump up^ “386 vs. 030: the Crowded Fast Lane”. Dr. Dobb’s Journal, January 1988.

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